Skip to Main Content
Itanium® Architecture for Programmers: Understanding 64-Bit Processors and EPIC Principles
book

Itanium® Architecture for Programmers: Understanding 64-Bit Processors and EPIC Principles

by James S. Evans - Lawrence University, Gregory L. Trimper - viika
April 2003
Intermediate to advanced content levelIntermediate to advanced
576 pages
15h 13m
English
Pearson
Content preview from Itanium® Architecture for Programmers: Understanding 64-Bit Processors and EPIC Principles

Exercises

1:Four Itanium logical instructions directly correspond to four of the sixteen logical functions in Table 6-1. Write single Itanium instructions that compute some of the other logical functions.
2:Suppose that registers r2 and r3 contain the values 0x12345678 and 0x9abcdef0, respectively. What would be the results computed and stored in register r1 by each of the Itanium logical instructions?
3:Devise examples to show that andcm r1=r2,r3 does not produce r1 = r2 NAND r3.
4:What is the net result of the following instruction sequence?
xor    r23=r22,r23
xor    r22=r23,r22
xor    r23=r22,r23
5:When an immediate value is used in an Itanium logical instruction, state in words what can be said a priori about bits <63:8> of the result for: (a) and
Become an O’Reilly member and get unlimited access to this title plus top books and audiobooks from O’Reilly and nearly 200 top publishers, thousands of courses curated by job role, 150+ live events each month,
and much more.
Start your free trial

You might also like

ARM System Developer's Guide

ARM System Developer's Guide

Andrew Sloss, Dominic Symes, Chris Wright
Intel Xeon Phi Processor High Performance Programming, 2nd Edition

Intel Xeon Phi Processor High Performance Programming, 2nd Edition

James Jeffers, James Reinders, Avinash Sodani

Publisher Resources

ISBN: 0131013726Purchase book