Machine Learning Techniques for VLSI Chip Design

6Gate All Around MOSFETs-A Futuristic Approach

Ritu Yadav¹* and Kiran Ahuja²

¹ ECE Department, IK Gujaral Punjab Technical University, Jalandhar, India

² ECE Department, DAVIET, Jalandhar, India

Abstract

In this chapter, the history of semiconductor technology and its continuous development processes such as recent MOSFET technologies, the significance of scaling in CMOS technology, challenges in scaling, futuristic scaling method (technology booster) the introduction of high-K, circuit design, and device modeling techniques are discussed. Considering all these challenges in the current scenario, this study was undertaken with the key focus on reducing the leakage current, improv- ing the subthreshold slope, and developing immunity against the short channel effect by introducing the hetero di-electric oxide (combination of high-K (HfO₂ and TiO₂) and traditional SiO₂) in triple asymmetric metal gate by quantization approach. Advance multiple devices such as Gate-all-around can be effectively used to improve the performance of the device in terms of the chip design area, speed, and power by using work function engineering and dielectric engineering. The quantum effect on the gate-all-around device is also discussed in detail.

Keywords: Gate-all-around (GAA), Sub-threshold voltage (SV), DIBL, SCEs

6.1 Introduction

VLSI (very large-scale integration) is an advanced and emerging field in the semiconductor industry for circuit implantation, system-level design, and memory applications. ...