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Microcontroller Programming and Interfacing Texas Instruments MSP430 by Daniel J. Pack, Steven F. Barrett

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6.6. MSP430 CLOCK SYSTEM 177
100 %
50 %
(a)
25 %
(b)
100 %
Figure 6.2: Two signals with the same period but different duty cycles. Frame (a) shows a periodic signal
with a 50% duty cycle, and frame (b) displays a periodic signal with a 25% duty cycle.
cycle. Aside from motor speed control applications, PWM techniques are used in a wide variety of
applications.
6.6 MSP430 CLOCK SYSTEM
The architects of the MSP430 designed the controllers clock system to provide flexibility and
minimum power consumption based on intended applications. Note that the power consumption is
directly related to the oscillation speed of the clock. The higher the frequency of a clock signal, the
more power is used. For example, typical microcontroller applications require a high frequency clock
for the central processing unit but not for the input/output interface systems. Running input/output
subsystems based on a slower clock saves power.
There are three different clock signal sources available for the MSP430 and three separate
clock systems. We call the clock signal sources as the clock signal generators. The three clock signal
generators are the LFXT1CLK (low frequency crystal clock 1),the XT2CLK clock (external clock 2),
178 6. TIMER SYSTEMS
Batteries
DC
Motor
Switch
Figure 6.3: An example setup for controlling a DC motor.
and the DCOCLK (digitally controlled oscillator clock). Both the LFXT1CLK and XT2CLK clock
signal generators use external crystals connected via the XIN and XOUT pins for the LFXT1CLK
and the XT2IN and XT2OUT pins for the XT2CLK. The XT2CLK clock signal generator can
also be connected to an external high speed clock source.The DCOCLK clock signal generator does
not require any external connections. The DCOCLK clock is generated internally and is used as the
master clock for the MSP430. The advantage of using the DCOCLK clock signal generator is its
ability to stabilize quickly after it is turned on. It takes less than 6 usec after start up which allows
the controller to resume normal operation after repeated power downs and ups to maximize power
usage with minimum interruptions. The time base for the DCOCLK uses a resistor/capacitor (RC)
combination; however, its frequency may be stabilized using the Frequency Locked Loop (FLL)
system.
The System Clock Generator 0 (SCG0), System Clock Generator 1 (SCG1), Oscillator Off
(OSCOFF), and CPU Off (CPUOFF) bits in the Status Register (SRR2) register determine the
operation of the controller as shown in Table 6.1. Based on applications, one can configure the
operation of MSP430 to select one or more of the clock signal generators summarized below.
Low Frequency Crystal Clock 1 (LFXT1CLK): typically connected to 32 kHz watch crystal,
but can be connected to crystals with higher frequencies (450 kHz to 8 MHz).
Crystal 2 Clock (XT2CLK): high frequency oscillator ranging from 450 kHz to 8 MHz,
providing a high-speed clock source to MSP430.
Digitally Controlled Oscillator Clock (DCOCLK): internally generated clock. Used as the
clock source for the master clock by default.
6.6. MSP430 CLOCK SYSTEM 179
2II
2Q
'XW\&\FOH:DYHIRUP


2II
2Q
'XW\&\FOH:DYHIRUP


Figure 6.4: Two pulse-width-modulated signals with 25% and 75% duty cycles.
Note that not all MSP430 controllers have all three clock signal generators. For example, the
ez430 controllers only have the LFXT1CLK and the DCOCLK clock signal generators. Given
the three clock signal generators, there are three main microcontroller clocks that operate from the
signals fed by the three clock signal generators. They are the Master Clock (MCLK), Sub-Main
Clock (SMCLK), and the Auxiliary Clock (ACLK).The MCLK clock is the clock for the MSP430
central processing unit (CPU) and can use any of the three clock signal sources (LFXT1CLK,
XT2CLK,and DCOCLK), which can be selected using control register Basic Clock System Control
Register 2 (BCSCTL2).The SMCLK clock is mainly used for peripheral devices. One can configure
the clock signal source for the SMCLK clock as either the LFXT1CLK or the XT2CLK.The ACLK
clock is for peripheral devices, and the clock signal source is the LFXT1CLK clock signal generator.
For example, the ACLK or SMCLK clock can be used as the clock for the Timer_A and Timer_B
systems, which we present later in this chapter.
Figure 6.5 shows how the three clock signals, ACLK, MCLK, and SMCLK are generated
from the three clock signal generators. For the rest of the discussion in this section, please refer to

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