178 6. TIMER SYSTEMS
Figure 6.3: An example setup for controlling a DC motor.
and the DCOCLK (digitally controlled oscillator clock). Both the LFXT1CLK and XT2CLK clock
signal generators use external crystals connected via the XIN and XOUT pins for the LFXT1CLK
and the XT2IN and XT2OUT pins for the XT2CLK. The XT2CLK clock signal generator can
also be connected to an external high speed clock source.The DCOCLK clock signal generator does
not require any external connections. The DCOCLK clock is generated internally and is used as the
master clock for the MSP430. The advantage of using the DCOCLK clock signal generator is its
ability to stabilize quickly after it is turned on. It takes less than 6 usec after start up which allows
the controller to resume normal operation after repeated power downs and ups to maximize power
usage with minimum interruptions. The time base for the DCOCLK uses a resistor/capacitor (RC)
combination; however, its frequency may be stabilized using the Frequency Locked Loop (FLL)
The System Clock Generator 0 (SCG0), System Clock Generator 1 (SCG1), Oscillator Off
(OSCOFF), and CPU Off (CPUOFF) bits in the Status Register (SRR2) register determine the
operation of the controller as shown in Table 6.1. Based on applications, one can conﬁgure the
operation of MSP430 to select one or more of the clock signal generators summarized below.
• Low Frequency Crystal Clock 1 (LFXT1CLK): typically connected to 32 kHz watch crystal,
but can be connected to crystals with higher frequencies (450 kHz to 8 MHz).
• Crystal 2 Clock (XT2CLK): high frequency oscillator ranging from 450 kHz to 8 MHz,
providing a high-speed clock source to MSP430.
• Digitally Controlled Oscillator Clock (DCOCLK): internally generated clock. Used as the
clock source for the master clock by default.