6.7. MSP430 UNIFIED CLOCK SYSTEM 183
MCLK signal.The SFR Interrupt Enable Register 1 (IE1) is used to enable the interrupt associated
with the timer, shown in Figure 6.9. The corresponding ﬂag resides in Figure 6.10.
76 5 4 3 2 1 0
SFR Interrupt Enable Register 1 (IE1)
Figure 6.9: SFR Interrupt Enable Register 1.
Finally, MSP430 controllers have the clock fault safe feature that monitors the clock signals
of LFXT1CLK and XT2CLK. If the clock fault safe circuit does not detect any clock signal for
50 usec, the clock source for the MCLK clock automatically switches to the DCO, and an inter-
rupt is triggered if the OFIE bit in the IE1 register located at memory address $0000 is set. The
corresponding interrupt ﬂag, the OFIFG bit, is in the IFG1 register located at memory address
76 5 4 3 2 1 0
SFR Interrupt Flag Register 1 (IFG1)
Figure 6.10: SFR Interrupt Flag Register 1.
6.7 MSP430 UNIFIED CLOCK SYSTEM
Some variations of the MSP430 microcontroller are equipped with the Uniﬁed Clock System (UCS).
The UCS is discussed in the Power Management System chapter, Chapter A.5.
6.8 WATCHDOG TIMER
As the name implies, the primary purpose of the Watchdog timer is to watch for and prevent
software failure by forcing user code to refresh a designated control register periodically throughout
the execution of a program.The secondary purpose of the watchdog timer is to generate periodic time
intervals.By software failure,we mean the execution of unintended instructions by MSP430,whether
it is an unintended inﬁnite loop or a wrong segment of program being executed due to hardware
errors, programmer errors, or noise related malfunctions. We now present how we conﬁgure the
watchdog system to function as a software failure preventer and a periodic interval generator.