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Microcontroller Programming and Interfacing Texas Instruments MSP430 by Daniel J. Pack, Steven F. Barrett

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184 6. TIMER SYSTEMS
6.8.1 PROTECTING FROM SOFTWARE FAILURE
The Watchdog timer prevents software failure by enforcing the following rule.A 16-bit register,called
the Watchdog Count (WDTCNT) register, counts up at each clock cycle. When it reaches its limit,
the watchdog timer system initiates a Power Up Clear Reset (PUCR)
1
. Thus, your program must
clear the counter periodically before the counter reaches its limit. During normal program execution,
counter reset instructions may be placed strategically throughout the code. When the code executes
correctly, the Watchdog timer will be reset on a regular basis. However, if the code is not operating
correctly, the Watchdog timer will not be reset as required thus generating a flag or an interrupt. A
user can select the limit values as 64, 512, 8192, or 32,768 (default), which correspond to using the
WDTCNT register as a 6, 9, 13, or 15 bit counter, respectively. The source for the clock cycle can
be chosen either from the SMCLK (default) or the ACLK.
The function of the Watchdog timer is governed by programming the Watchdog Timer
Control Register (WDTCTL). To avoid accidental write to this register, it is password protected,
which means to modify the contents of the register, one must first write 0x5A (password) to the
upper byte of WDTCTL before configuring the Watchdog system using the lower byte of the same
register. MSP430 designers also implemented another safety mechanism by resetting the controller
if a wrong password is sent to the upper byte of WDTCTL. Figure 6.11 shows the contents of the
16-bit register. As discussed, the high byte of the register is reserved as a password to access this
register.
WatchDog Timer Register (WDTCTL)
Read as 069h
WDTPW must be written as 05Ah
76 5 4 3 2
1
0
WDTHOLD
WDTNMIES
WDTNMI WDTTMSEL WDTCNTCL
WDTSSEL WDTISx
rw-0 rw-0 rw-0 rw-0 r0(w) rw-0 rw-0 rw-0
15 14 13 12 11 10 9 8
Figure 6.11: Watchdog Timer Register WDTCTL.
The 7th bit (WDTHOLD) is used to turn-on or turn-off the watchdog timer. Setting this bit
disables the Watchdog counter, and clearing this bit configures the system to function normally. Bits
6 and 5 are not used. Bit 4 (WDTTMSEL) determines the mode of operation for the Watchdog
timer: setting this bit selects the interval timer mode while clearing this bit designates the Watchdog
mode. Writing a logic one to bit 3 (WDTCNTCL) clears the counter. This is how your program
can prevent the Watchdog Timer from generating a PUCR. Once the WDTCNT is cleared, this
bit is reset (0) automatically. The WDTSSEL bit (bit 2) selects the clock source for the counter.
1
Unlike the Power-On Reset (POR), the Power Up Clear Reset (PUCR) does not change the values of the WDTCTL register.

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