O'Reilly logo

Microcontroller Programming and Interfacing Texas Instruments MSP430 by Daniel J. Pack, Steven F. Barrett

Stay ahead with the world's most comprehensive technology and business learning platform.

With Safari, you learn the way you learn best. Get unlimited access to videos, live online training, learning paths, books, tutorials, and more.

Start Free Trial

No credit card required

6.8. WATCHDOG TIMER 185
Setting this bit chooses the ACLK clock while clearing this bit selects the SMCLK clock. Finally,
WDTISx bits (bits 1 and 0) are used to select the Watchdog timer reset periods as shown below:
00 - use 15 bit counter and count up to 32,768
01 - use 13 bit counter and count up to 8,192
10 - use 9 bit counter and count up to 512
11 - use 6 bit counter and count up to 64
The default value of the register selects the 15 bit counter using the SMCLK clock as the time
source.
Associated with the control register is the IFG1 register. When the WDTCNT register
reaches its limit, the WDTIFG flag (bit 0) in the IFG1 register, located at 0x0002, is set. This flag
can be polled or can be used to initiate an interrupt when the Watchdog timer is used as a periodic
interval timer.
Example: The following C code or the corresponding assembly code turns off the watchdog timer,
which is recommended during program development.Assuming that the registers are already defined,
the Watchdog timer may be turned off using the following C instruction:
WDTCTL = WDTPW + WDTHOLD
In Assembly Language, use:
MOV.W #WDTPW+WDTHOLD, &WDTCTL
6.8.2 INTERVAL TIMER
The Watchdog timer can also be configured to generate a periodic interval.To do so, the WDTTM-
SEL bit (bit 4) of the WDTCTL register must be set and the interval period must be selected using
the WDTISx bits (bits 1 and 0) and the WDTSSEL bit (bit 2) of the same register. When the
WDTCNT register reaches the designated limit, the WDTIFG flag in the IFG1 register is set. If
the WDTIE bit (bit 0) in the Interrupt Enable IE1 register 1 (IE1) is set and the GIE bit (overall
maskable interrupt system enable bit in the Status Register) is set, the Watchdog timer interrupt is
triggered. Figure 6.12 shows the components of the interval timer along with the related interrupt
system. Once the interrupt is serviced (interrupt service routine is executed), the WDTIFG flag is
automatically cleared.
Example: Provided below is the assembly code segment followed by the C code segment that
configures the MSP430x20x3 microcontroller to toggle the logic state on port 1 pin 0 every 250
msec. We assume that the LFX1CLK clock signal generator is connected to watch crystal running
at 32kHz and ACLK is driven by the LFX1CLK clock signal generator. This code would execute
on the ez430-F2013 USB Stick Development Tool discussed in Chapter A.5. This example code is
available for other MSP430 families at www.TI.com.
186 6. TIMER SYSTEMS
WDTCNT
WDTSSEL
SMCLK
ACLK
WDTIFG
Watchdog
Interrupt
System
limit reached
WDTIE
GIE
Figure 6.12: Watchdog Timer as an Interval Generator.
;************************************************************************
;MSP430x20x3 Watchdog timer (WDT) demonstration
;Toggle P1.0, Interval Overflow ISR, 32kHz ACLK
;
;Description: Toggle P1.0 using software timed by WDT interrupt service
;routine (ISR). The toggle rate is 250ms based on 32kHz ACLK WDT clock
;source. In this example, the WDT is configured to divide a 32768 Hz
;watch crystal by 2ˆ13 with an ISR triggered at 4 Hz.
;
;An external watch crystal is required at pins XIN and XOUT
;for the ACLK source. (ACLK = LFXT1 = 32768Hz, MCLK = SMCLK = DCO)
;
;P.Thanigai
;Texas Instruments Inc.
;May 2007
;Built with Code Composer Essentials Version: 2.0
;************************************************************************
.cdecls C,LIST, "msp430x20x3.h"
;------------------------------------------------------------------------
6.8. WATCHDOG TIMER 187
.text ;Program Start
;------------------------------------------------------------------------
RESET mov.w #0280h,SP ;Initialize stackpointer
Setup mov.w #WDT_ADLY_250,&WDTCTL ;WDT 250ms, ACLK, int timer
bis.b #WDTIE,&IE1 ;Enable WDT interrupt
SetupP1 bis.b #001h,&P1DIR ;P1.0 output
;
Mainloop bis.w #LPM3+GIE,SR ;Enter LPM3, interrupt enable
nop ;Required only for debugger
;
;------------------------------------------------------------------------
WDT_ISR; Toggle P1.0
;------------------------------------------------------------------------
xor.b #001h,&P1OUT ;Toggle P1.0
reti ;
;
;------------------------------------------------------------------------
; Interrupt Vectors
;------------------------------------------------------------------------
.sect ".reset" ;MSP430 RESET Vector
.short RESET ;
.sect ".int10" ;WDT Vector
.short WDT_ISR ;
.end
;------------------------------------------------------------------------
In C:
//***********************************************************************
//MSP430F20xx Demo - WDT, Toggle P1.0, Interval Overflow ISR,
//32kHz ACLK
//
//Description: Toggle P1.0 using software timed by WDT ISR. Toggle rate
//is 250ms based on 32kHz ACLK WDT clock source. In this example, the
//WDT is configured to divide 32768 watch-crystal by 2ˆ13 with an ISR
//triggered at 4Hz.
//
//An external watch crystal is installed on XIN XOUT for the ACLK.
//(ACLK = LFXT1 = 32768Hz, MCLK = SMCLK = default DCO)
//

With Safari, you learn the way you learn best. Get unlimited access to videos, live online training, learning paths, books, interactive tutorials, and more.

Start Free Trial

No credit card required