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Microcontroller Programming and Interfacing Texas Instruments MSP430 by Daniel J. Pack, Steven F. Barrett

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202 6. TIMER SYSTEMS
contents are compared with the contents of the free running counter, and when a match occurs, the
programmed logic state appears on the designated hardware pin. Once the rising edge is generated,
the program then must reconfigure the event to be a falling edge (logic state low) and change the
contents of the special register to be compared with the free running counter. For the particular
example in Figure 6.16, lets assume that the main clock runs at 2 MHz, the free running counter is
a 16 bit counter, and the name of the special register (16 bit register) where we can put appropriate
values is output timer register. To generate the desired pulse, we can put $0000 first to the output
timer register, and after the rising edge has been generated, we need to change the program event to
a falling edge and put $0FA0 or 4000 in decimal to the output timer register. As was the case with
the input timer system module, we can use output timer system interrupts to generate the desired
signals as well.
6.10.3 MSP430 TIMERS
All MSP430 microcontrollers have both Timer_A and Timer_B input/output ports that can be
used to capture external signal events and generate time related signals for external devices. The
captured external signal events include time stamped logic state changes, the frequency of a periodic
signal, a width of a pulse to name a few. The time related output signals range from a simple
change of logic levels on an output pin at a designated time to generation of pulse width modulated
(PWM) signals. We present both input capture and output compare subsystem capabilities in this
section. Both Timer_A and Timer_B systems can be configured to function as capture and compare
input/output ports. The Timer_A system is present in all MSP430 controllers while Timer_B, with
more advanced capture and compare capabilities, is found in larger MSP430 family members. We
start our discussion with the Timer_A system.
6.10.4 MSP430 FREE RUNNING COUNTER
Within the Timer_A system, there are two to three different input/output subsystems (channels)
that can be configured independently. For the Timer_B system, the number of input/output channels
vary from three to seven. Since each channel for Timer_A and Timer_B systems has the identical
hardware and functional capabilities, we present only a single channel for each timer system. The
source of all timer subsystems, whether they are used to capture input signal characteristics or to
generate output time-related signals, is a free running 16-bit counter, the TAxR register.The counter
counts up (can count down for some applications) at a specified interval, determined by the clock
source used and a pre-scalar factor, and works as the universal timer for all time-related events.
Figure 6.17 shows the free running counter, TAxR, and the features that govern its operation. The
programming of the counter is done with the help of the Timer_A control register (TACTL).
Figure 6.18 shows the contents of the 16 bit register. Referring to Figure 6.17 and Figure 6.18
together, one can use bits 9 and 8 (TASSELx) of the TACTL register to choose the clock used for
the free running counter as follows.
00 - TACTL (external clock)
6.10. INPUT CAPTURE AND OUTPUT COMPARE FEATURES 203
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Figure 6.18: Timer_A Control Register.
The Input Divider (IDx) bits (bits 7 and 6 in the TACTL register) are used to scale the clock source
before the free running counter updates itself. The pre-scale factors are
00 - increase (decrease) the TAR counter by one at each (rising/falling edge) clock cycle.
01 - increase (decrease) the TAR counter by one every two clock cycles.
10 - increase (decrease) the TAR counter by one every four clock cycles.

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