O'Reilly logo

Microcontroller Programming and Interfacing Texas Instruments MSP430 by Daniel J. Pack, Steven F. Barrett

Stay ahead with the world's most comprehensive technology and business learning platform.

With Safari, you learn the way you learn best. Get unlimited access to videos, live online training, learning paths, books, tutorials, and more.

Start Free Trial

No credit card required

6.10. INPUT CAPTURE AND OUTPUT COMPARE FEATURES 207
mov.w #0000, &TACCR0 ;setup TACCR0
mov.w #CCIE+CM_3, &TACCTL0 ;capture both edges (CM_3)
;CCR0 interrupt enabled
mov.w #TASSEL_3+MC_1,&TACTL ;setup counter for up mode
bis.b #02, &Flag ;setup flag for two events
loop tst Flag ;two events?
jez pulse ;jump to compute pulse width
jmp loop ;wait for second pulse
pulse sub &Second, &First ;compute the time difference
;-----------------------------------------------------------------------
TA0_ISR
dec Flag ;event occurred
tst Flag
jez Two ;second event
mov.w TACCR0, &First ;store the first event time
jmp Done
Two mov.w TACCR0, &Second ;store the second event time
Done reti
;------------------------------------------------------------------------
6.10.6 OUTPUT COMPARE
In this subsection, we present the function opposite to the input capture capabilities. The output
compare function is designed to generate desired time critical signals on an output pin. To do so,
MSP430 architects designed the compare channels using almost the same registers used in the
input capture systems previously described. Refer to Figure 6.21 and Figure 6.20 for the following
discussion. At each clock cycle, the comparator compares the current value in the TAR with the one
previously stored in the TACCRx register. When the two values match (identical), the output logic
state (either logic high or logic low) will appear on the output pin based on the programmed states
of OUTMODx bits (bits 7,6, and 5) of the TACCTLx register as shown below:
000 - output logic is controlled by the OUT bit (bit 2)
001 - set the logic on the output pin high (continuous counting mode)
010 - toggle the logic state on the output pin (Up/Down counting mode)
011 - set or resets the logic state on the output pin (Up counting mode)
100 - toggle the logic state on the output pin (continuous counting mode)
208 6. TIMER SYSTEMS
&&,)*[
&RPSDUH
,QWHUUXSW
6\VWHP
&&,
*,(
28702'[
7$&&5[
7$5
&RPSDUDWRU
/DWFK
287[
(48
(48
Figure 6.21: Output Compare Diagram.
101 - reset (logic zero) the logic state on the output pin (continuous counting mode)
110 - toggle the logic state on the output pin (Up/Down counting mode)
111 - set or reset the logic state on the output pin (Up counting mode)
The EQU0 signal, shown in Figure 6.21, governs modes 010, 011, 110, and 111. When the com-
parison of values in TACCRx and TAR results in a match, the CCIFG flag is also set (logic 1), and
if the CCI bit along with the GIE bit is set, the corresponding output compare interrupt system is
enabled. One can also use more than one channel to generate a periodic pulse. By directing the out-
put signal onto a single output pin and configuring two channels, say channel 0 with TACCR0 and
channel 1 with TARCCR1, appropriately, one can generate a periodic signal. For example, suppose
we configure both channels to be output compare channels, output event to set and reset the output
logic state. If we assume continuous counting mode from 0x0000 to 0xFFFF for the free running
counter, by setting the TACCR0 value to be zero and the TACCR1 value to be 0x8000, we can
generate a pulse width modulated signal with 50 % duty cycle. One can also achieve the same output
signal using a single channel, say channel 0, setting the output mode to toggle the logic states. Note
that the frequency of the signal is half of the signal generated using two channels.
In the remainder of this section, we show how register TAIV (Timer_A Interrupt Vector)
is used to configure a desired interrupt service routine. The first column of Table 6.2 shows the
values need to be loaded to the TAIV register to program a particular interrupt system. The second
column of the same table shows the corresponding interrupt source for the numerical values shown
in the first column. When an interrupt occurs, the appropriate interrupt service routine must clear
the associated flag of the interrupt, shown in the last column of the table.

With Safari, you learn the way you learn best. Get unlimited access to videos, live online training, learning paths, books, interactive tutorials, and more.

Start Free Trial

No credit card required