208 6. TIMER SYSTEMS
Figure 6.21: Output Compare Diagram.
• 101 - reset (logic zero) the logic state on the output pin (continuous counting mode)
• 110 - toggle the logic state on the output pin (Up/Down counting mode)
• 111 - set or reset the logic state on the output pin (Up counting mode)
The EQU0 signal, shown in Figure 6.21, governs modes 010, 011, 110, and 111. When the com-
parison of values in TACCRx and TAR results in a match, the CCIFG ﬂag is also set (logic 1), and
if the CCI bit along with the GIE bit is set, the corresponding output compare interrupt system is
enabled. One can also use more than one channel to generate a periodic pulse. By directing the out-
put signal onto a single output pin and conﬁguring two channels, say channel 0 with TACCR0 and
channel 1 with TARCCR1, appropriately, one can generate a periodic signal. For example, suppose
we conﬁgure both channels to be output compare channels, output event to set and reset the output
logic state. If we assume continuous counting mode from 0x0000 to 0xFFFF for the free running
counter, by setting the TACCR0 value to be zero and the TACCR1 value to be 0x8000, we can
generate a pulse width modulated signal with 50 % duty cycle. One can also achieve the same output
signal using a single channel, say channel 0, setting the output mode to toggle the logic states. Note
that the frequency of the signal is half of the signal generated using two channels.
In the remainder of this section, we show how register TAIV (Timer_A Interrupt Vector)
is used to conﬁgure a desired interrupt service routine. The ﬁrst column of Table 6.2 shows the
values need to be loaded to the TAIV register to program a particular interrupt system. The second
column of the same table shows the corresponding interrupt source for the numerical values shown
in the ﬁrst column. When an interrupt occurs, the appropriate interrupt service routine must clear
the associated ﬂag of the interrupt, shown in the last column of the table.