O'Reilly logo

Microcontroller Programming and Interfacing Texas Instruments MSP430 by Daniel J. Pack, Steven F. Barrett

Stay ahead with the world's most comprehensive technology and business learning platform.

With Safari, you learn the way you learn best. Get unlimited access to videos, live online training, learning paths, books, tutorials, and more.

Start Free Trial

No credit card required

6.10. INPUT CAPTURE AND OUTPUT COMPARE FEATURES 211
while(1) //wait for interrupt to occur
{
;
}
}
//Timer_A TACCR0 interrupt service routine
Interrupt(TIMERA0_VECTOR) TimerA_procedure(void)
{
P1OUT ˆ= 0x01; //toggle logic state
}
6.10.7 TIMER_B SYSTEM
The Timer_B system can be used as input capture and output compare timer units as we have done
with the Timer_A system. It contains three to seven different subsystems (channels) that can be
configured as capture or compare systems. The primary difference between Timer_A and Timer_B
system is that an extra buffer is introduced in the Timer_B system along with a means to update
the value of the register used to compare the free running timer value when a channel is used as an
output compare system and to capture the free running counter value when configured as an input
capture system.
Figure 6.22 shows the extra buffer used in Timer_B systems. Note that the free running
counter is now called TBR instead of TAR as you saw in the previous section.The TACCRx register
is replaced by two 16 bit registers TBCLx and TBCCRx. When a Timer_B channel is configured
as an input capture channel and a programmed event appears on the input pin, the free running
counter value is captured in the TBCCRx register as was the case in the Timer_A system, but you
have an option to upload that value into another 16-bit register, TBCLx. Why do you need this
extra register? Suppose you have external events that occur very quickly and you need to capture
both events. By loading the first event time and storing it quickly will allow the TBCCRx register
to be free to capture the second event. Similarly, when a channel is configured as an output compare
channel, the extra register allows a programmer to generate output signals whose time values are
separated by a ’small number
4
. Referring to Figure 6.22, note that the CCLDx bits (bits 10 and 9)
of the TBCCTLx register govern the time when the value from the TBCCRx register is transferred
to the TBCLx register as shown below.
00 - immediate
01 - update when TBR value is zero
10 - same as 01 for continuous up count mode. If Up/Down count mode is chosen, the transfer
occurs either when TBR =0 or TBCLx = TBR
4
The small free running counter difference value is governed by the time required to upload a new value from TBCCRx to TBCLx.
212 6. TIMER SYSTEMS
11 - update when TBR = old TBCLx
7%&/[
7%5
&RPSDUDWRU
7%&&5[
&//'[
8SGDWH
Figure 6.22: Timer_B additional components.
Before we leave this section, we show an example program that uses the capabilities of the
Timer_B system of the MSP430F22x4 controller to generate two pulse-width modulated signals
on port P1.0 and P1.1. Both signals have 50% duty cycles which can be easily modified. The output
ports are P4 pins 1 and 2. The program utilizes the counting up mode along with the TBCCR0,
TBCCR1, and TBCCR2 systems to generate the pulses. The duration specified by the contents
of the TBCCR0 register determines the pulse period while the values in TBCCR1 and TBCCR2
registers determine the duty cycles for the two pulses. For our example, the two values in TBCCR1
and TBCCR2 are the same, but if different duty cycles are desired, these values should be changed
proportional to the value stored in the TBCCR0 register. We assume that the ACLK clock is
connected to the LFX1CLK clock signal generator with 32kHz crystal.
;-----------------------------------------------------------------------
bis.b #06h,&P4DIR ;setup P4.1 and P4.2 as output
bis.b #06h,&P4SEL ;P4.1 and P4.2 TB1-2 options
mov.w #8000h, &TBCCR0 ;PWM period
mov.w #OUTMOD_7, &TBCCTL1 ;TBCCR1 reset/set
mov.w #4000h, &TBCCR1 ;TBCCR1 PWM duty cycle
mov.w #OUTMOD_7, &TBCCTL2 ;TBCCR2 PWM duty cycle
mov.w #TBSSEL_1+MC_1, &TBCTL ;ACLK, up mode
loop jmp loop ;wait

With Safari, you learn the way you learn best. Get unlimited access to videos, live online training, learning paths, books, interactive tutorials, and more.

Start Free Trial

No credit card required