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Microcontroller Programming and Interfacing Texas Instruments MSP430 by Daniel J. Pack, Steven F. Barrett

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6.11. LABORATORY EXERCISE: GENERATION OF VARYING PULSE WIDTH 213
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6.11 LABORATORY EXERCISE: GENERATION OF VARYING
PULSE WIDTH MODULATED SIGNALS TO CONTROL
DC MOTORS
Purpose: The purpose of this laboratory exercise is to program an MSP430 series controller to
generate a pulse-width modulated signal/waveform with varying duty cycle to control the speed of
a DC motor. The program requires you to use the input capture and output compare capabilities of
the controller. To meet the requirements of this laboratory exercise, you must
Use the output compare system to modify the duty cycle of the output waveform,
Use the input capture system to monitor the number of pulses generated by the output compare
system and adjust the output waveform appropriately,
Change the duty cycle based on a desired DC motor speed profile,
Configure Port 1 pins, and
Verify the output waveform by connecting the output pin on Port 1 to an oscilloscope.
Documentation: User Manual of your MSP430 microcontroller board
Prelab: For the prelab, complete a flowchart and pseudocode for your program.
Description: As we learned in this chapter, the timer system of the MSP430 series microcon-
troller is used for signal generation, measurement, and timing. In this lab, you are asked to configure
an MSP430 series controller to generate desired output waveforms using its output compare system.
The contents of the output compare system registers are programmed to set and clear the logic states
of an output pin and cause an interrupt related to the output pin.
The output event occurs when the free running counter (TAR) value matches the value stored
in the designated output compare register (TACCRx). By adjusting the value in the TACCRx
register, one can program MSP430 to change the time when an output event occurs. The input
capture system is used to monitor the incoming signal. In this laboratory exercise, it is used to count
the number of pulses being generated by the output compare pin. By counting the number of pulses,
the input capture system can keep track of the time the output waveform is generated and modify
the duty cycle accordingly. The physical pins used in this laboratory are P1.1 and P1.2, where P1.1
will be used as the input capture pin and the P1.2 pin will be used as the output compare pin.
Tasks: In this lab, you need to write a program to modify the duty cycle of an output periodic
signal in real-time. The desired speed profile (velocity versus time) is shown in Figure 6.23. The
y-axis shows the desired duty cycle, and the x-axis shows the time duration for the entire profile.The
duty cycle should increase from 0% to 50% during the first three seconds, maintain the 50% duty
214 6. TIMER SYSTEMS
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Figure 6.23: Desired speed profile for the DC motor.
cycle for another 3 seconds, and decrease to 0% duty cycle during the last three second period. The
waveform period is 32 msec (This is the default time for the TAR register to count from 0 to 65,536.).
You must generate approximately 457, 32 msec pulses. The duty cycle should increase linearly from
0% to 50% in 3 seconds, or in 152 pulses. Using P1.2 pin as the output pin, the TACCR2 register
value should change from 0000h to 8000h in 152 pulses or by adding approximately 216 counts to
the TACCR2 register at each pulse.
Procedure To generate the desired pulse width modulated signal, use P1.2 pin as the output compare
pin and P1.1 as the input capture pin.
Turn on the Timer System.
Turn off the Watchdog Timer.
Generate the pulse width modulated signal.
Set the logic states on the output pin to be low (off) when successful compares are made
by configuring bits in the TACCTL2 register.
Use the TACCR0 system to set logic state high (on) the pulse using the TACCTL0
register.
Set up the duty cycle.
We are using the square wave period of 32 msec. We can find a corresponding number
that represents a desired duty cycle. For example, 8000h represents 50% duty cycle. When
8000h is stored in the TACCR2 register and the TAR register value matches with the
one in TACCR2, the designated action (logic off ) takes place on the output pin.

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