O'Reilly logo

Microcontroller Programming and Interfacing Texas Instruments MSP430 by Daniel J. Pack, Steven F. Barrett

Stay ahead with the world's most comprehensive technology and business learning platform.

With Safari, you learn the way you learn best. Get unlimited access to videos, live online training, learning paths, books, tutorials, and more.

Start Free Trial

No credit card required

7.4. MSP430 RESETS 221
level indication. The maskable interrupts, as the name indicates, are those requests, if necessary, that
can be masked (ignored) by the CPU. The maskable interrupts require a programmer to activate the
interrupts by writing to specific registers.
7.4 MSP430 RESETS
The Brownout reset is triggered by four different events. The first one occurs when power is applied
to the controller when it was turned off. One can simulate the power up event also by supplying
a low signal to the
RT S/NMI pin, which is the second event. The RT S/NMI pin is configured
as the reset pin as the default setting designated with the SYSNMI bit in the SFRRPCR (Special
Function Register Reset Pin Control Register) shown in Figure 7.1. Note that a programmer can also
configure the pin to enable and disable (SYSRSTRE Reset pin resistor enable and SYSRSTUP
Reset resistor pin pullup/pulldown) pullup or pulldown registers connected to the pin as well as
assigning a particular logic level (SYSNMIEES NMI edge select bit) to trigger the reset using this
register. This pin is connected to the reset button on all of the MSP430 evaluation boards. The third
possible event that can cause the BOR is when the MSP430 controller wakes up from operating
mode LPM3.5 or LPM4.5. Finally, the last event that triggers the BOR is software BOR events.
For some applications, it is desired to trigger a Brownout reset using a software instruction. Setting
PMMSWBOR (Power Management Module SoftWare BOR) bit in the PMMCTL0 register
(Power Management Module Control Register 0) initiates a software generated BOR.
6\VWHP)XQFWLRQ5HJLVWHU5HVHW3LQ&RQWURO5HJLVWHU6)553&5DW
5HVHUYHG5HVHUYHG5HVHUYHG5HVHUYHG 5HVHUYHG
5HVHUYHG
5HVHUYHG5HVHUYHG
UUUUUUUU

5HVHUYHG 5HVHUYHG5HVHUYHG5HVHUYHG 6<65675( 6<656783 6<610,,(6 6<610,
UUUUUZUZUZUZ

Figure 7.1: Special Function Register Reset Pin Control Register.
The second type of reset, the Power-On Reset (POR), is automatically triggered when the
BOR occurs as shown in Figure 7.2. The POR is typically associated with the hardware system
while the Power-Up Clear (PUC) reset is generally linked to software events. In addition to a BOR
event, the POR is triggered by the Power Management Module (PMM) when it detects the power
level of the controller (Supply Voltage Supervisor) falls below a threshold value or a software POR
event. The PUC reset is initiated by six events. The first one is the POR event. Whenever the
controller detects a POR, the PUC reset is also triggered. The second and the third reset events for
222 7. RESETS AND INTERRUPTS
the PUC reset are associated with the Watchdog Timer System. When the Watchdog Timer expires
or the Watchdog Timer password is violated, the PUC reset is triggered. The remaining events are
the password violation to access the onboard flash memory, password violation to access the Power
Management Module, and fetching from memory areas not populated.
1
A password to access the
flash memory is necessary to prevent a runaway program from corrupting stored software.
to active mode
Figure 7.2: Reset activity of the MSP430 microcontroller. Figure used with permission of Texas Instru-
ments.
Thus, the BOR initializes all systems while the POR and the PUC resets restore MSP430
conditions partially in that order. Throughout the documents for the MSP430 microcontroller, one
finds the POR and PUC reset values annotated using symbols such as rw-(1 or 0). For example,
rw-0 indicates that the register bit value can be read or written and the initial value is 0 after the
PUC reset, while rw-(0) denotes that the register bit can be read and written and the initial value
is 0 after the POR. For the latter example case, the register value remains the same after the PUC
reset. The general conditions of the MSP430 microcontroller after a reset are:
the
RT S/NMI pin is configured as the reset mode,
all input and output pins are configured as input,
1
The VMAIE (Vacant memory access interrupt enable flag) bit must be set(1) for this reset to initiate.

With Safari, you learn the way you learn best. Get unlimited access to videos, live online training, learning paths, books, interactive tutorials, and more.

Start Free Trial

No credit card required