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Microcontroller Programming and Interfacing Texas Instruments MSP430 by Daniel J. Pack, Steven F. Barrett

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7.5. INTERRUPTS 223
the program counter register is loaded with the boot code start address (ex. 0xFFFE),
the status register (SR) is cleared,
all peripheral modules and registers are initialized, and the
Watchdog Timer is initialized (Watchdog Mode).
Due to the steps taken by the MSP430 microcontroller after a reset, the programmer must
make sure that, at the start of the proper program module, the stack pointer, the watchdog specifi-
cations, and peripheral modules are initialized.
7.5 INTERRUPTS
A microcontroller normally executes instructions in an orderly fetch-decode-execute sequence as
dictated by a user-written program as shown in Figure 7.3. However, the microcontroller must
be equipped to handle unscheduled, higher priority events that might occur inside or outside the
microcontroller. To process such events, a microcontroller requires an interrupt system.
The interrupt system onboard a microcontroller allows it to respond to higher priority events.
These events may be planned, but we do not know when they will occur. When an interrupt event
occurs, the microcontroller will normally complete the instruction it is currently executing and then
transition program control to interrupt event specific tasks. These tasks, which resolve the interrupt
event, are organized into a function called an interrupt service routine (ISR). Each interrupt will
normally have its own interrupt specific ISR. Once the ISR is complete, the microcontroller will
resume processing where it left off before the interrupt event occurred.
Applying the general concept of an interrupt, one can consider resets as interrupts with one
exception. Resets do not return to the original task and instead resets the controller while after an
interrupt service routine a controller resumes execution of the task just before the interrupt was
detected. Thus, with the understanding of the difference between resets and interrupts, resets may
be categorized as non-maskable interrupts (NMI).
Besides resets, there are two other types of NMIs supported by MSP430 microcontroller. The
first type is the system generated NMIs (SNMI), and the second type are the ones generated by
the user (UNMI). One example of an SNMI type interrupt, is the JTAG mailbox event. Recall that
the JTAG interface is available for all MSP430 microcontrollers for the purpose of programming,
debugging and testing the MSP430.The JTAG interface allows access to the CPU during program
execution. One can configure the interface such that when data is read through the interface, a non-
maskable interrupt occurs.The second and third types of SNMIs come from the Power Management
Module when either supply voltage level is not reached or the time expired before the voltage levels
settle down to designated values. These two power related SNMIs were discussed in Chapter A.5.
The last type of SNMI is caused by accessing a vacant memory location.
For the user specified NMIs, there are three sources that can generate an UNMI.The first one
is associated with access violation of flash memory. The second one is caused by an oscillator fault.
224 7. RESETS AND INTERRUPTS
Fetch
Decode
Execute
Interrupt
Service
Routine
Figure 7.3: Microcontroller interrupt response.
The controller monitors the crystal oscillator frequency. An UNMI is triggered when the frequency
falls outside an acceptable range. The third and final UNMI is caused by the logic state on the
RT S/NMI pin when the pin is configured for the NMI mode.
The MSP430 microcontroller has many maskable interrupt (MIs) sources. The difference
between NMIs and MIs is that unlike NMIs, maskable interrupts can be ignored by the CPU, if
the Global Interrupt Enable (GIE) bit of the status register is turned off. To enable a maskable
interrupt, not only must the GIE bit must be set, but each subsystem interrupt in use must also
be enabled. These subsystems are enabled using appropriate bits in the interrupt enable register
(SFRIE1), shown in Figure 7.4. When one of these interrupts occurs, the corresponding flag in the
interrupt flag register (SFRIFG1), shown in Figure 7.5, is set.
In most microcontrollers,including the MSP430,the starting address for each interrupt service
routine, the special function to perform the service, is stored in a pre-designated location which the
CPU recognizes. These locations are located in consecutive memory locations and are collectively
designated interrupt vectors. For the MSP430 microcontroller, they are located at memory locations
0xFFFF through 0xFF80 where each vector takes up two memory locations. Memory space is

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