7.5. INTERRUPTS 225
$&&9,( 10,,( 90$,(
Figure 7.4: Interrupt Enable Register.
provided in the interrupt vector table for up to 64 different interrupt sources. Figure 7.6 provides
the table of interrupt vectors for MSP430 microcontroller.
During the development phase, it is handy to conﬁgure the top of RAM space as alternative
locations for interrupt vectors by setting the SYSRIVECT (RAM-based interrupt vectors) bit in
the System Control Register (SYSCTL) register, shown in Figure 7.7.
7.5.1 INTERRUPT HANDLING PROCESS
In this subsection, we describe the process of handling an interrupt event. Once a maskable interrupt
is conﬁgured to be active, and an interrupt event occurs, a ﬂag that corresponds to the particular
interrupt event is asserted to indicate to the CPU that there is an interrupt waiting to be serviced.
The CPU then takes the following actions in the order shown to provide an orderly transition from
normal program operation to the interrupt service routine and back again.
1. Complete the current instruction
2. Store the contents of the Program Counter onto the stack
3. Store the contents of the Status Register onto the stack