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Microcontroller Programming and Interfacing Texas Instruments MSP430 by Daniel J. Pack, Steven F. Barrett

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Figure 7.4: Interrupt Enable Register.
provided in the interrupt vector table for up to 64 different interrupt sources. Figure 7.6 provides
the table of interrupt vectors for MSP430 microcontroller.
During the development phase, it is handy to configure the top of RAM space as alternative
locations for interrupt vectors by setting the SYSRIVECT (RAM-based interrupt vectors) bit in
the System Control Register (SYSCTL) register, shown in Figure 7.7.
7.5.1 INTERRUPT HANDLING PROCESS
In this subsection, we describe the process of handling an interrupt event. Once a maskable interrupt
is configured to be active, and an interrupt event occurs, a flag that corresponds to the particular
interrupt event is asserted to indicate to the CPU that there is an interrupt waiting to be serviced.
The CPU then takes the following actions in the order shown to provide an orderly transition from
normal program operation to the interrupt service routine and back again.
1. Complete the current instruction
2. Store the contents of the Program Counter onto the stack
3. Store the contents of the Status Register onto the stack
226 7. RESETS AND INTERRUPTS
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Figure 7.5: Interrupt Flag Register.
4. Choose the highest priority interrupt if multiple interrupts are pending
5. Reset the interrupt request flag
6. Clear the Status Register to prevent additional interrupts from occurring and to switch from
the low power mode to the normal power mode (if configured)
7. Load the contents of the interrupt vector onto the program counter (PC)
8. Execute the specified interrupt service routine
9. Once the service routine is finished (with the RETI instruction), restore the SR and then PC
values from the stack
10. Resume normal operation
Typically, it takes six clock cycles for the MSP controller before the interrupt processing starts
once an interrupt is detected, and it takes five clock cycles to restore the SR and PC values and
resume executing normally after the interrupt service ends. Figure 7.8 shows the stack configuration
before and after step 3 and step 9.
Following the procedure described above, everything would be straight forward if for each
interrupt source, there was only a single and unique interrupt flag. Unfortunately, that is not always
7.5. INTERRUPTS 227
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Figure 7.6: MSP430 Interrupt Vector Table.
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Figure 7.7: System Control Register.
the case for MSP430 microcontroller. For example, for all interrupts associated with the Timer_A
module, a single flag, TAIFG (Timer_A interrupt flag), is set. It becomes a programmer’s responsi-
bility to resolve the ambiguity as a part of the interrupt service routine by checking the TAIV register
(Timer_A Interrupt Vector Register), which contains a value identifying the interrupt source. Sim-
ilarly, the source of a non-maskable interrupt or a reset is resolved with the help of three interrupt
vector registers: SYSRSTIV (Reset Interrupt Vector register), SYSSNIV (System NMI Vector reg-
ister), and SYSUNIV (User NMI Vector register). When a reset occurs, based on the source, it
generates an interrupt vector offset value in the SYSRSTIV register as shown in Figure 7.9.

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