228 7. RESETS AND INTERRUPTS
Figure 7.8: Stack before and after an interrupt.
The SYSRSTVEC bits (Reset interrupt vectors – bits 1 through 5) determine the interrupt
vector offset value. Similarly, the SYSSNIV and the SYSUNIV registers are used to identify the
source of an interrupt. See Figures 7.10 and 7.11. For example, when dealing with a user non-
maskable interrupt, as the ﬁrst step of the service routine, the contents of the SYSUNIV and PC are
added as shown in Figure 7.12. The offset value governs the execution of the appropriate portion
of the interrupt service routine.
When MSP430 microcontroller is shipped, the interrupt service routines for resets and system
non-maskable interrupts are already programmed and should not be altered. We described the above
process to illustrate a similar process to resolve the source of a non-maskable user interrupt or
maskable interrupt in your interrupt service routine. We should also note that some devices have
separate bus error interrupts, which can also be serviced in the same manner as shown above using
the SYSBERRIV (Bus Error Interrupt Vector) register.
7.5.2 INTERRUPT PRIORITY
As shown in Figure 7.6, there are multiple reset and interrupt sources associated with the MSP430
microcontroller. Priorities among interrupts must be deﬁned in advance to handle situations when
more than one interrupt occurs simultaneously. The MSP430 microcontroller sets the priority in
the following manner. The resets hold the highest priority, followed by the system NMIs, the
user NMIs, and the device speciﬁc maskable interrupts. Figure 7.13 shows the priority list for the
MSP430F5438 microcontroller. The corresponding offset vector values for the interrupts using the
SYSRSTIV, SYSSNIV, and SYSUNIV registers are shown in Figure 7.14. Since each version of the
MSP430 controller has a different number of interrupts associated with its subsystems, one should
always consult the datasheet for the particular controller to ﬁnd the interrupt priority list.