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Microcontroller Programming and Interfacing Texas Instruments MSP430 by Daniel J. Pack, Steven F. Barrett

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7.5. INTERRUPTS 229
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Figure 7.9: Reset Interrupt Vector Register.
A typical MSP430 microcontroller configuration has built-in interrupt systems for a Direct
Memory Access (DMA) controller, a Digital-to-Analog Converter(DAC), an Analog Comparator
(Comp_B), digital input/output ports (P1 and P2), one or more Timer_A system, a Timer_B system,
a Real Time Clock A (RTC_A) system, a Real Time Clock B (RTC_B) system, Analog-to-Digital
Converter (ADC), a UART system, and a USB system. Since it requires a detailed understanding
of each system to use the associated interrupt, we defer the discussion of each interrupt system to
chapters that cover the subsystems.
7.5.3 INTERRUPT SERVICE ROUTINE (ISR)
Most of the interrupt handling process described in this chapter takes place automatically (you, as
a programmer, do not need to program them). In fact, for the resets, all processing is completed
230 7. RESETS AND INTERRUPTS
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Figure 7.10: System Non-Maskable Interrupt Vector Register.
automatically. For maskable interrupts; however, your responsibility as a programmer is to (1) turn
on the Global Interrupt Enable (GIE), (2) initialize the stack pointer, (3) configure the interrupt
vector table (initialize the start address of your ISR), (4) enable the appropriate interrupt local enable
bit (SFRIE1 register), and (5) write the corresponding interrupt service routine. In this subsection,
we present the last task, writing an ISR.
Examples: In this example, we write an ISR using the Timer_A interrupt system. Recall that all
Timer_A system related interrupts have the same interrupt vector. Thus, a Timer_A ISR must
identify the source before executing a desired task. In MSP430x5xx related microcontrollers, the
Timer_A system contains seven separate input and output channels: channels 0 through 6, where
channels 1 through 6 have the same interrupt vector table entry.Assume that all six channel interrupts
are enabled, using assembly language, we can write an ISR similar to the one provided in Figure 7.12.
The ISR is shown in Figure 7.15.
The next example shows how to implement a Timer_A related ISR. Note how the ISR is
configured. The code snapshot below shows how to tie the starting address of the ISR to the proper
7.5. INTERRUPTS 231
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Figure 7.11: User Non-maskable Interrupt Vector Register.
location in the ISR. Definitions for all MSP430F5438 related interrupts are provided in Appendix
B.
#pragma vector=TIMER1_A1_VECTOR
__interrupt void TIMER1_A1_ISR(void)
Also note in the following example how multiple MSP430F5338 Timer_A related ISRs are
mapped using a case statement. In this example, only a single Timer_A related ISR is employed.
//***********************************************************************
//MSP430F54x Demo - Timer_A3, Toggle P1.0, Overflow ISR, DCO SMCLK
//
//Description: Toggle P1.0 using software and Timer1_A overflow ISR.
//In this example an ISR triggers when TA overflows. Inside the TA
//overflow ISR P1.0 is toggled. Toggle rate is approximately 16.8Hz.
//Proper use of the TAIV interrupt vector generator is demonstrated.
//ACLK = n/a, MCLK = SMCLK = TACLK = default DCO ˜1.05MHz
//
//M Smertneck / W. Goh
//Texas Instruments Inc.
//September 2008
232 7. RESETS AND INTERRUPTS
61,B,65 $'' 6661,93& $GGRIIVHWWRMXPSWDEOH
5(7, 1RLQWHUUXSW
-03 690/B,65 YHFWRU
-03 690+B,65 YHFWRU
-03 690+9B,65 YHFWRU
,QYDOLGB,65 5(7, YHFWRU
690/B,65 ,65IRUYHFWRU
5(7,
690+B,65 ,65IRUYHFWRU
5(7,
690+9B,65 ,65IRUYHFWRU
5(7,
Figure 7.12: Sample ISR for User Non-maskable Interrupts.
//Built with CCE Version: 3.2.2 and IAR Embedded Workbench Version: 4.11B
//***********************************************************************
#include "msp430x54x.h"
void main(void)
{
WDTCTL = WDTPW + WDTHOLD; //Stop WDT
P1DIR |= 0x01; //P1.0 output
TA1CTL = TASSEL_2 + MC_2 + TACLR + TAIE; //SMCLK, contmode, clear TAR
//enable interrupt
__bis_SR_register(LPM0_bits + GIE); //Enter LPM0, enable interrupts
__no_operation(); // For debugger
}
//***********************************************************************
// Timer_A3 Interrupt Vector (TAIV) handler
#pragma vector=TIMER1_A1_VECTOR
__interrupt void TIMER1_A1_ISR(void)
{
switch(__even_in_range(TA1IV,14))
{
7.5. INTERRUPTS 233
,QWHUUXSWV $VVRFLDWHG)ODJV 7\SH $GGUHVV 3ULRULW\
3RZHUXSH[WHUQDOUHVHW :'7,)*.(<96<6567,9 5HVHW )))(K +LJKHVW
:DWFKGRJWLPHRXW
:DWFKGRJSDVVZRUG
YLRODWLRQ)ODVKPHPRU\
SDVVZRUGYLRODWLRQ
300SDVVZRUGYLRODWLRQ
3009DFDQWPHPRU\ 690/,)*690+,)*'/</,)* 6\VWHP )))&K
DFFHVV-7$*PDLOER[ '/<+,)*9/5/,)*9/5+,*) 1RQPDVNDEOH
90$,)*-0%1,)*-0%287,*+
6<661,9
10,2VFLOODWRUIDXOW 10,,)*2),)*$&&9,)* 8VHU )))$K
)ODVKPHPRU\DFFHVV 6<681,9 1RQPDVNDEOH
YLRODWLRQ
7% 7%&&52&&,)* 0DVNDEOH )))K
7% 7%&&5&&,)*7%&&5&&,5* 0DVNDEOH )))K
7%,)*7%,9
:DWFKGRJ7LPHUB$ :'7,)* 0DVNDEOH )))K
,QWHUQDOWLPHUPRGH
86&,B$UHFHLYHWUDQVPLW 8&$5;,5)8&$7;,)*8&$,9 0DVNDEOH )))K
86&,B% UHFHLYHWUDQVPLW 8&%5;,5)8&%7;,)*8&$%,9 0DVNDEOH )))K
$'&B$ $'&,)*$'&,)* 0DVNDEOH ))((K
7$ 7$&&5&&,)* 0DVNDEOH ))(&K
7$ 7$&&5&&,)*7$&&5&&,)* 0DVNDEOH ))($K
7$,)*7$,9
86&,B$ UHFHLYHWUDQVPLW 8&$5;,)*8&$7;,)*8&$,9 0DVNDEOH ))(K
86&,B% UHFHLYHUWUDQVPLW 8&%5;,)*8&%7;,)*8&%,9 0DVNDEOH ))(K
'0$ 0'$,)*'0$,)*'0$,)* 0DVNDEOH ))(K
'0$,9
7$ 7$&&5&&,)* 0DVNDEOH ))(K
7$ 7$&&5&&,)*7$&&5&&,)* 0DVNDEOH ))(K
7$)*7$,9
3 3,)*WR3,)*3,9 0DVNDEOH ))'(K
86&,B$UHFHLYHWUDQVPLW 8&$5;,)*8&$7;,)*8&$,9 0DVNDEOH ))'&K
86&,B% UHFHLYHWUDQVPLW 8&%5;,)*8&%7;,)*8&%,9 0DVNDEOH ))'$K
86&,B$ UHFHLYHWUDQVPLW 8&$5;,)*8&$7;,)*8&$,9 0DVNDEOH ))'K
86&,B% UHFHLYHWUDQVPLW 8&%5;,)*8&%7;,)*8&%,9 0DVNDEOH ))'K
3 3,)*WR3,)* 0DVNDEOH ))'K
57&B$ 57&5'<,)*57&7(9,)*57&$,)* 0DVNDEOH ))'K
57236,)*5736,)*57&,9
5HVHUYHG 5HVHUYHG ))'K))K /RZHVW
Figure 7.13: Interrupt Priority List for MSP430F5438.

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