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Microcontroller Programming and Interfacing Texas Instruments MSP430 by Daniel J. Pack, Steven F. Barrett

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260 8. ANALOG PERIPHERALS
8.6 MSP430 DIGITAL-TO-ANALOG CONVERTER
Certain models of the MSP430 microcontroller have one or two identical digital to analog converters.
The converter can operate in either an 8 bit or 12 bit mode, which is determined by the DAC12RES
bit in the DAC12 Control Register 0 (DAC12_xCTL0). The x in the DAC12_xCTL0 register is
either 0 or 1 to indicate with which of the two possible converters the control register is associated.
Selecting inputs as 8 or 12 bits determines the level of resolution one would use to issue the output
voltage of the DAC converter. The control register can be modified only when the DAC12ENC bit
is set. For the rest of the discussion of the converter, refer to Figure 8.8.
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Figure 8.8: A block diagram of the MSP430 12-bit digital-to-analog converter.
We start with the converter inputs shown on the bottom of the figure.The format of the input
can be programmed as unsigned or 2’s complement (both negative and positive) numbers. This is
done using the DAC12DF bit in the DAC12_xCTL0 register: 0 - unsigned binary value and 1 -
2’s complement value. You can also right justify or left justify inputs using the DAC12DJ bit in the
same control register: 0 - right justified and 1 - left justified.
The converter can either take 12 or 8 bit inputs directly or using a latch. For the binary format,
the lowest and highest analog output values are mapped to input values of 0000h and 0FFFh (12
bit) or 00FFh (8 bit), respectively. When the 2’s complement format is used, the smallest and the
largest analog output values are 0800h (12 bits) or 0080 (8 bits) and 07FFh (12 bits) or 007Fh (8
bits). The DAC12LSELx bits (bits 11-10) of the DAC12_xCTL0 register, shown on the bottom
left of the figure, determine when the contents of the data register (DAC12_xDAT) are sent to the
converter. Table 8.3 shows the possible configurations.
Thus, selecting the two bits to 00 the contents of the DAC12_xDAT register are immediately
available to the DAC12 latch register, DAC12_xLATCH, and the converter. When these bits are
8.6. MSP430 DIGITAL-TO-ANALOG CONVERTER 261
Table 8.3:
DAC12LSELx (bits 11 and 10) DAC load selection
00 DAC latch loads when DAC12_xDAT is written
01 DAC latch loads when DAC12_xDAT is written
01 or when all DAC12_xDAT registers are written
10
DAC latch loads with rising edge of Timer_A.OUT1
11 DAC latch loads with rising edge of Timer_B.OUT2
01, an input must be written to the DAT12_xDAT register for the data to be latched and be available
to the converter. When the bits are 10 or 11, the data are latched with a rising edge on the TA1 or
TB2 pin. In addition, for the latter three cases (DAC12LSELx = 01,10, and 11), the DAC12ENC
bit must be set to latch new input data. The DAC12GRP bit is used to group DAC12 converters:
setting this bit of DAC12_0CTL0 register groups converters DAC12_0 and DAC12_1. One would
group DAC modules when output synchronization is necessary. The DAC12ENC bit enables (1)
or disables (0) the converter when DAC12LSELx bits are 01, 10, or 11.
We now describe the upper half of Figure 8.8. The previous discussion of the converter
determines the input digital value format (signed or unsigned, left or right justified, and 8-bit or
12-bit operation) and the time when input values become available to the converter. The upper
portion of the figure describes how the output analog voltage range can be configured. The positive
reference voltage (the maximum digital-to-analog converter output value) can be configured to be
the output (1.5V, 2.0V, or 2.5V) of the REF module, the analog positive source voltage (AVcc),
or an external reference voltage based on the selection of the DAC12SREFx bits (bits 14-13)
of the DAC12_xCTL0 register, shown on the top left of the figure. The DAC12IR bit in the
DAC12_xCTL0 register and the DAC12OG bit in the DAC12_xCTL1 register determine the
output voltage range as follows.
DAC12OG DAC12IR Converter O u tput
0 0 full-scale output=3xrefvoltage
1
0 full-scale output=2xrefvoltage
x 1 full-scale output=1xrefvoltage
The DAC12AMPx bits (bits 7-5) of the DAC12_xCTL0 register are used to control settling
time and power consumption. The higher the number, the faster the speed of the conversion and
the higher the current consumption, thus power, required to operate.
To increase the accuracy of the output of the converter, the designer of the MSP430 controllers
provided means to calibrate the digital-to-analog converter output. Setting the DACD12CALON
bit in the DAC12_xCTL0 register initiates a calibration process. Before a calibration is per-
formed, one must first unlock the LOCK bit in the DAC12 Calibration Control Register
(DAC12xCALCTL) by writing password A5h to the upper 8 bits of the DAC12_xCALCTL
register. Writing the password to the control register clears and locks the LOCK bit. With the lock

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