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Microcontroller Programming and Interfacing Texas Instruments MSP430 by Daniel J. Pack, Steven F. Barrett

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274 9. COMMUNICATION SYSTEMS
Support for serial transmission protocols including the capability to transmit 7 or 8 bit data
with odd, even, or no parity.
Independent transmit and receive shift registers equipped with separate transmit and receive
buffer registers.
The capability to send or receive data the least significant bit (LSB) first or the most signifi-
cant bit (MSB) on both the transmit and receive channels. This feature allows the MSP430
microcontroller to match the protocol of an existing peripheral device.
The capability to operate within a multiprocessor system using the built-in idle-line and
address-bit communication protocols.
Auto wake up feature from a low power mode (LPMx) when a start edge is received.
Extensive flexibility in setting programmable baud rates.
A number of system status flags for error detection, error suppression, and address detection.
Interrupts for the data receive and transmit.
In the next section, we examine how these features are incorporated into the UART hardware.
9.3.2 UART OVERVIEW
Provided in Figure 9.3 is a block diagram of the UCSI_Ax module configured for UART mode
(UCSYNC bit = 0). The UART module can be subdivided into the Baudrate Generator (center of
Figure 9.3), the receiver related hardware (top of figure), and the transmit hardware (lower portion
of figure). We discuss each in turn.
The USCI_Ax module communicates asynchronously with another device (e.g., peripheral)
when the UCSYNC mode is set to zero. As previously mentioned, in an asynchronous mode, the
transmitter and receiver maintain synchronization with one another, using start and stop bits to
frame each data byte sent. It is essential that both transmitter and receiver are configured with the
same Baud rate, number of start and stop bits, and the type of parity employed (odd, even or none.)
The Baud rate is set using the Baudrate generator in the center of Figure 9.3.The clock source
for the Baudrate generator may either be the UCAxCLK, the ACLK, or the SMCLK. The clock
source is selected using the USCI clock source select bits (UCSSELx) located in the USCI_Ax
Control Register 1 (UCAxCTL1).The source selected becomes the Baudrate clock (BRCLK). The
Baudrate clock may then be prescaled and divided to set the Baud rate for the transmit and receive
clock.
The receive portion of the UART system is in the upper portion of Figure 9.3. Serial data
is received via the UCAxRXD pin. The serial data is routed into the Receive Shift Register when
the UCLISTEN bit located within the USCI_Ax Status Register (UCAxSTAT) is set to zero. If
required by the specific application, the data may first be routed through the IrDA Decoder.
9.3. MSP430 UART 275
Figure 9.3: Block diagram of the UCSI_Ax module configured for UART mode (UCSYNC bit = 0)
[slau208g].

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