276 9. COMMUNICATION SYSTEMS
The conﬁguration of the Receive Shift Register is set by several bits located within the
USCU_Ax Control Register 0 (UCAxCTL0). These include the:
• Parity enable bit, UCPEN (0: parity disabled, 1: parity enabled)
• Parity select bit, UCPAR (0: odd parity, 1: even parity)
• MSB ﬁrst select, UCMSB (0: LSB ﬁrst, 1: MSB ﬁrst)
• Character length bit, UC7BIT (0: 8-bit data, 1: 7-bit data)
The Receive State Machine controls the operation of the receive associated hardware. It has
control bits to:
• Select the number of stop bits, UCSPB (0: one stop bit, 1: two stop bits)
• Select the USCI mode, UCMODEx (00: UART mode)
• Select the synchronous mode, UCSYNC (0: asynchronous mode, 1: synchronous mode).
The hardware associated with serial data transmission is very similar to the receive hardware
with the direction of data routed for transmission out of the UCAxTXD pin.
9.3.3 CHARACTER FORMAT
As previously mentioned, the UART system has great ﬂexibility in setting the protocol of the serial
data, including the number of bits (7 or 8), parity (even, odd, or none), MSB or LSB ﬁrst, and
selection of transmit/receive operation. A typical serial data word is illustrated in Figure 9.4.To
verify the valid functionality of the serial communication using the MSP430 microcontroller, it is
very helpful to write a short program to transmit the same piece of data continuously from the
UART and observe the transmission on the UCAxTXD pin with an oscilloscope or a logic analyzer.
(7 or 8)
Figure 9.4: UART serial data format. [slau208g].
9.3.4 BAUD RATE SELECTION
The MSP microcontroller also has considerable ﬂexibility in setting the Baud rate for UART trans-
mission and reception. It has two different modes for Baud rate generation: