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Microcontroller Programming and Interfacing Texas Instruments MSP430 by Daniel J. Pack, Steven F. Barrett

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9.3. MSP430 UART 277
Low frequency Baud rate generation (UCOS16, Oversampling Mode Enable bit = 0). The
mode allows Baud rates to be set when the microcontroller is being clocked by a low frequency
clock. It is advantageous to do this to reduce power consumption by using a lower frequency
time base. In this mode, the Baudrate Generator uses a prescaler and a modulator to generate
the desired Baud rate. The maximum selectable Baud rate in this mode is limited to one-third
of the Baud rate clock (BRCLK).
Oversampling Baud rate generation (UCOS16 = 1). This mode employs a prescaler and a
modulator to generate higher sampling frequencies.
To set a specific Baud rate, the following parameters must be determined:
The clock prescaler setting (UCBRx) in the Baud Rate Control Register 0 and 1 (USAxBR0
and UCAxBR0) must be determined. The 16-bit value of the UCBRx prescaler value is
determined by UCAxBR0 + UCAxBR1 × 256.
First, modulation stage setting, UCBRFx bits in the USCI_Ax Modulation Control Register
(UCAxMCTL).
Second,modulation stage setting,UCBRSx bits in the USCI_Ax Modulation Control Register
(UCAxMCTL).
The documentation for a specific MSP430 microcontroller contains extensive tables for de-
termining the UCBRx, UCBRFx and UCBRSx bit settings for various combinations of the Baud
rate clock (BRCLK) and desired Baud rate.
9.3.5 UART ASSOCIATED INTERRUPTS
The UART system has two associated interrupts. The Transmit Interrupt Flag (UCTXIFG) is set
when the UCAxTXBUF is empty, indicating another data byte may be sent.The Receive Interrupt
Flag (UCRXIFG) is set when the receive buffer (UCAxRXBUF) has received a complete character.
Both of these interrupt flags are contained within the USCI_Ax Interrupt Flag Register (UCAxIFG).
9.3.6 UART REGISTERS
As discussed throughout this section, the basic features of the UART system is configured and
controlled by the following UART related registers:
USCI_Ax Control Register 0 (UCAxCTL0)
USCI_Ax Control Register 1 (UCAxCTL1)
USCI_Ax Baud Rate Control Register 0 (UCAxBR0)
USCI_Ax Baud Rate Control Register 1 (UCAxBR1)

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