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Microcontroller Programming and Interfacing Texas Instruments MSP430 by Daniel J. Pack, Steven F. Barrett

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284 9. COMMUNICATION SYSTEMS
Slave Out Master In (UCxSOMI) pin of the slave device and into the UCxSOMI pin of the master
device. After eight master UCxCLK clock pulses, a byte of data has been exchanged between the
master and slave designated SPI devices. Completion of data transmission in the master and data
reception in the slave is signaled by SPI related interrupts in both devices. At that time, another data
byte may be transmitted.
MSB LSB
MSP430 USCI
Master Device
Slave Device
MOSI
MISO
SPI Bit Clock Generator
Baud rate
clock
SPI Data Register (SDR)
MSB LSB
SCK
UCxCLK
SCK
SS
shift
enable
USCI_Ax Control Register 0 (UCAxCTL0)
USCI_Bx Control Register 0 (UCBxCTL0)
USCI_Ax Control Register 1 (UCAxCTL1)
USCI_Bx Control Register 1 (UCBxCTL1)
USCI_Ax Bit Rate Control Register 0 (UCAxBR0)
USCI_Bx Bit Rate Control Register 0 (UCBxBR0)
USCI_Ax Bit Rate Control Register 1 (UCAxBR1)
USCI_Bx Bit Rate Control Register 1 (UCBxBR1)
USCI_Ax Modulation Control Register (UCAxMCTL)
USCI_Ax Status Register (UCAxSTAT)
USCI_Bx Status Register (UCBxSTAT)
Status Registers
Control Registers
UCxSTE
UCxCLK
Transmit Shift Register
Transmit Buffer (UCxTXBUF)
UCxSIMO
UCxSOMI
Figure 9.5: SPI Overview.
9.4.2 MSP430 SPI FEATURES
As previously mentioned, the MSP430 SPI system has many features that allow the system to be
interfaced to a wide variety of SPI configured devices. These features include:
7-bit or 8-bit data length
LSB-first or MSB-first data transmit and receive capability
3 or 4 wire SPI operation
Master or slave modes
Independent transmit and receive shift registers which provide continuous transmit and receive
operation

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