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Microcontroller Programming and Interfacing Texas Instruments MSP430 by Daniel J. Pack, Steven F. Barrett

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9.4. SERIAL PERIPHERAL INTERFACE—SPI 285
Selectable clock polarity and phase control
Programmable clock frequency in master mode
Independent interrupt capability for receive and transmit
9.4.3 MSP430 SPI HARDWARE CONFIGURATION
The MSP430 provides support for SPI communication in both of the USCI_A and USCI_B
modules. A block diagram of an UCSI module configured for SPI operation is shown in Figure 9.6.
SPI operation is selected by setting the UCSYNC (Synchronous mode enable) bit to logic one in
the module’s USCI_Ax or USCI_Bx Control Register 0 (UCAxCTL0 or UCBxCTL0).
Beginning in the center of the diagram, the clock source for the SPI Baud rate clock (BR-
CLK) may either be provided by the ACLK or the SMCLK. The clock source is chosen using the
USCI clock source select (UCSSELx) bits in USCI_Ax (or B) Control Register 1 (UCAxCTL1 or
UCBxCTL1).
The Baud rate clock is fed to the Bit Clock Generator. The 16 bit clock prescaler is formed
using (UCxxBR0 + UCxxBR1 x 256). The values for UCxxBR0 and UCxxBR1 are contained
in the USCI_xx Bit Rate Control Registers 0 and 1 (UCxxBR0 and UCxxBR1).
The MSP430 USCI provides the flexibility to configure the SPI data transmission format
to match that of many different peripheral devices. Either seven or eight bit data format may be
selected using the UC7BIT. Also, the phase and polarity of the data stream may be adjusted to
match peripheral devices. The polarity setting determines active high or low transmission while the
polarity bit determines if the signal is asserted in the first half of the bit frame or in the second
half. Furthermore, the data may be transmitted with the least significant bit (LSB) first or the
most significant bit (MSB) first. In summary, the serial data stream format is configured using the
following bits in the USCI_Ax (or Bx) Control Register 0 (UCAxCTL0):
UCCCPH: clock phase select 0: data changed on the first UCLK edge and captured on
the following edge, 1: data captured on the first edge and changed on the second edge
UCCKPL: clock polarity select — 0: inactive state low, 1: inactive state high
UCMSB: MSB first select — 0: LSB transmitted first, 1: MSB transmitted first
UC7BIT: character length select – 0: 8-bit data, 1: 7-bit data
The clock signal is routed from the Bit Clock Generator to both the receive state machine and
the transmit state machine.To transmit data,the data is loaded to theTransmit Buffer (UCxTXBUF).
Writing to the UCxTXBUF activates the bit clock generator. The data begins to transmit. Also, the
SPI system receives data when the transmission is active.The transmit and receive operations occur
simultaneously.
The SPI system is also equipped with interrupts. The UXTXIFG interrupt flag in the
USCI_Ax (or Bx) Interrupt Flag Register (UCAxIFG, UCBxIFG) is set when the UCxxTXBUF is
286 9. COMMUNICATION SYSTEMS
Figure 9.6: SPI hardware overview [slau208g].

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