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Microcontroller Programming and Interfacing Texas Instruments MSP430 by Daniel J. Pack, Steven F. Barrett

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292 9. COMMUNICATION SYSTEMS
USCI_A0_ISR
;------------------------------------------------------------------------
; Echo back RXed character, confirm TX buffer is ready first
add.w &UCA0IV,PC
reti ;Vector0-nointerrupt
jmp RXIFG_HND ;Vector 2 - RXIFG
reti ;Vector 4 - TXIFG
RXIFG_HND
wait_TX_rdy bit.b #UCTXIFG,&UCA0IFG ;USCI_A0 TX buffer ready?
jnc wait_TX_rdy
mov.b &UCA0RXBUF,&UCA0TXBUF ;RXBUF -> TXBUF
reti ;Return from interrupt
;------------------------------------------------------------------------
; Interrupt Vectors
;------------------------------------------------------------------------
.sect ".int57"
.short USCI_A0_ISR
.sect ".reset" ;POR, ext.
Reset
.short RESET
.end
;------------------------------------------------------------------------
In C, the master is configured with the following code:
//***********************************************************************
//MSP430F54x Demo - USCI_A0, SPI 3-Wire Master Incremented Data
//
//Description: SPI master talks to SPI slave using 3-wire mode.
//Incrementing data is sent by the master starting at 0x01. Received data
//is expected to be same as the previous transmission. USCI RX ISR is
//used to handle communication with the CPU, normally in LPM0. If high,
//P1.0 indicate valid data reception. Because all execution after LPM0
//is in ISRs, initialization waits for DCO to stabilize against ACLK.
// ACLK = ˜32.768kHz, MCLK = SMCLK = DCO ˜ 1048kHz. BRCLK = SMCLK/2
//
//Use with SPI Slave Data Echo code example.
//
// MSP430F5438
9.4. SERIAL PERIPHERAL INTERFACE—SPI 293
// -----------------
// /|\| |
// | | |
// --|RST P1.0|-> LED
// | |
// | P3.4|-> Data Out (UCA0SIMO)
// | |
// | P3.5|<- Data In (UCA0SOMI)
// | |
// Slave reset <-|P1.1 P3.0|-> Serial Clock Out (UCA0CLK)
//
//
//W. Goh
//Texas Instruments Inc.
//November 2008
//Built with CCE Version: 3.2.2 and IAR Embedded Workbench Version: 4.11B
//***********************************************************************
#include "msp430x54x.h"
unsigned char MST_Data,SLV_Data;
void main(void)
{
WDTCTL = WDTPW+WDTHOLD; //Stop watchdog timer
P1OUT |= 0x02; //Set P1.0 for LED
//Set P1.1 for slave reset
P1DIR |= 0x03; //Set P1.0-2 to output dir
P3SEL |= 0x31; //P3.5,4,0 option select
UCA0CTL1 |= UCSWRST; //Put state machine in reset
UCA0CTL0 |= UCMST+UCSYNC+UCCKPL+UCMSB; //3-pin, 8-bit SPI master
//Clock polarity high, MSB
UCA0CTL1 |= UCSSEL_2; //SMCLK
UCA0BR0 = 0x02; ///2
UCA0BR1 = 0; //
UCA0MCTL = 0; //No modulation
UCA0CTL1 &= ˜UCSWRST; //Init USCI state machine
294 9. COMMUNICATION SYSTEMS
UCA0IE |= UCRXIE; //Enable USCI_A0 RX interrupt
P1OUT &= ˜0x02; //Now with SPI signals init,
P1OUT |= 0x02; //reset slave
__delay_cycles(100); //Wait for slave to init
MST_Data = 0x01; //Initialize data values
SLV_Data = 0x00; //
while (!(UCA0IFG&UCTXIFG)); //USCI_A0 TX buffer ready?
UCA0TXBUF = MST_Data; //Transmit first character
__bis_SR_register(LPM0_bits + GIE); //CPU off, enable interrupts
}
#pragma vector=USCI_A0_VECTOR
__interrupt void USCI_A0_ISR(void)
{
switch(__even_in_range(UCA0IV,4))
{
case 0: break; //Vector0-nointerrupt
case 2: //Vector 2 - RXIFG
while (!(UCA0IFG&UCTXIFG)); //USCI_A0 TX buffer ready?
if (UCA0RXBUF==SLV_Data) //Test for correct char RX’d
P1OUT |= 0x01; //If correct, light LED
else
P1OUT &= ˜0x01; //If incorrect, clear LED
MST_Data++; //Increment data
SLV_Data++;
UCA0TXBUF = MST_Data; //Send next value
__delay_cycles(40); //Add time between
//transmissions to
//make sure slave can process
//information
break;
9.4. SERIAL PERIPHERAL INTERFACE—SPI 295
case 4: break; //Vector 4 - TXIFG
default: break;
}
}
//***********************************************************************
In C, the slave is configured with the following code:
//***********************************************************************
//MSP430F54x Demo - USCI_A0, SPI 3-Wire Slave Data Echo
//
//Description: SPI slave talks to SPI master using 3-wire mode. Data
//received from master is echoed back. USCI RX ISR is used to handle
//communication, CPU normally in LPM4. Prior to initial data exchange,
//master pulses slaves RST for complete reset.
// ACLK = ˜32.768kHz, MCLK = SMCLK = DCO ˜ 1048kHz
//
//Use with SPI Master Incremented Data code example.
//
// MSP430F5438
// -----------------
// /|\ | |
// | | |
// Master---+->|RST P1.0|-> LED
// | |
// | P3.4|-> Data Out (UCA0SIMO)
// | |
// | P3.5|<- Data In (UCA0SOMI)
// | |
// | P3.0|-> Serial Clock Out (UCA0CLK)
//
//
//W. Goh
//Texas Instruments Inc.
//October 2008
//Built with CCE Version: 3.2.2 and IAR Embedded Workbench Version: 4.11B
//***********************************************************************
#include "msp430x54x.h"
void main(void)

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