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Microcontroller Programming and Interfacing Texas Instruments MSP430 by Daniel J. Pack, Steven F. Barrett

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298 9. COMMUNICATION SYSTEMS
The communication performed on the I
2
C bus must follow a set of agreed rules, including the
data format used on the bus. Data is transferred between devices connected on the bus in 8 bits per
segment, followed by control bits. For each communication ’session,’ it must be started by a master
device with a start condition, which is defined as the signal changing from logic high to low on the
SDA line while the logic state on the SCL line is high. Following the start condition, the master
device must send either the 7 or 10 bit address of a destination device on the SDA line.
Following the address, the master device sends a Read/Write bit describing its intent and
listens on the bus to hear an acknowledge bit from the receiver on the 9th SCL clock for the 7-bit
addressing mode or on the both 9th and 18th clocks for the 10-it addressing mode.
For the 10-bit addressing mode, the 10-bit address is split into two segments: two most
significant bits (MSBs) and eight least significant bits (LSBs). The MSBs are sent along with pre-
designated bits (11110), and the LSBs are sent separately. After the first part of the address is sent, a
Read/Write bit, followed by an acknowledgment bit, must appear on the bus before the second part
of the address is sent. After the second part of the address, an acknowledgement bit must appear
before data is sent over the bus. Figure 9.7 shows the format of data transfer between two devices,
using both the 7-bit and the 10-bit addressing modes. For each communication session, it must end
with a stop condition (P in the figure), which is defined as the signal state on the SDA line changing
from logic low to logic high while the clock signal on the SCL line is high.
9.5.1 MSP430 AS A SLAVE DEVICE
The MSP430 microcontroller can also be configured to be either as a slave device or as a master
device.To configure the controller as a slave device, the USCI_Bx ports must first be programmed to
operate in the I
2
C slave mode (UCMODEx = 11, UCSYNC = 1, UCMST = 0). The slave address
of MSP430 is defined using UCBxI2COA register. The UCA10 bit in the UCBx Control Register
0 (UCBxCTL0) determines whether the controller is using a 7-bit address or a 10-bit address.
You can program the MSP430 microcontroller to respond to a general call by setting the
general call response enable bit (UCGCEN) in the UCBxI2COA register.To receive device addresses
sent by masters, the USCI_Bx ports must also be configured in the receiver mode (UCTR = 0).When
the start condition is detected on the bus, the address bits are compared, and if there is a match, the
UCSTTIFG flag is set.
After testing that the Read/Write bit is high, MSP430 uses the clock signal on the SLK
line to send data on the SDA line. To do so, the UCTR and UCTXIFG bits are set while holding
the SCL line logic low. While the logic state on the SCL line is low, the transmit buffer register
(UCBxTXBUF) is loaded with data. Once the buffer is loaded, the UCSTTIFG flag is cleared,
which sends the data out to the SDA line, and the UCTXIFG flag is automatically set again for
the next data to be transmitted, which occurs after an acknowledge bit is detected on the bus. If the
not-acknowledge (NACK) bit is detected, followed by a stop condition, instead, the UCSTPIFG
flag is set. If the NACK bit is detected followed by a start condition, MSP430 starts to monitor this
device address, again, on the SDA line.

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