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Microcontroller Programming and Interfacing Texas Instruments MSP430 by Daniel J. Pack, Steven F. Barrett

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9.5. INTER-INTEGRATED COMMUNICATION - I
2
C MODULE 299
If the MSP430 controller should receive data from a slave device (the Read/Write bit is low),
the UCTR bit is cleared, the receive buffer (UCBxRXBUF) is loaded with the data from the bus,
and the UCRXIFG flag is set, acknowledging the receipt of the data. Once the data in the bus is
read, the flag is cleared, and the controller is ready to receive the next 8-bit data. The controller has
an option to send the UCTXNACK bit to a master to release the bus. When a stop condition is
detected on the bus, the UCSTPIFG flag is set. If two repeated start conditions are detected or the
UCSTPIFG flag is set, the MSP430 terminates its current session and starts monitoring its address
on the bus.
9.5.2 MSP430 AS A MASTER DEVICE
To configure the MSP430 controller to function as a master device, the USCI_Bx ports must
be programmed to operate in the I
2
C mode (UCMODEx = 11, UCSYNC = 1), and one must
configure the MSP430 to operate in the master mode by setting the UCMST bit. Since the I
2
C
bus can handle more than one master device and if there are multiple master devices, the MSP430
needs to be programmed as one of many master devices on the bus by setting the UCMM bit and
storing the address (either 7 or 10 bits) of MSP430 in the UCBxI2COA register. As in the case of
the slave mode, the address size is determined by the UCA10 bit, and the general call response is
programmed using the UCGCEN bit.
To initiate a session to transmit data, the UCTR bit and the UCTxSTT bit are set, the
UCSLA10 bit is configured to match the slave address size, and the address of a slave device is
loaded to the UCBxI2CSA. When the start condition is generated by setting the UCTxSTT bit,
the data can be loaded to the UCBxTXBUF, and the UCTxIFG bit is set. Once a slave address
acknowledges its address, the UCTxSTT and UCTxIFG bits are cleared. Once the data is sent,
the UCTxIFG flag bit is set, again, for the next set of data transfer. To generate a stop condition,
set UCTxSTP bit while UCTxIFG and UCTxSTP bits are set. If a repeated start conditions are
necessary, set UCTxSTT bit. During a data transfer session, if a slave does not respond (i.e., send
acknowledge bits), the MSP430 must either send a stop condition or a repeated start conditions.
When the MSP430 controller needs to receive data from a slave, the UCTR bit must be
cleared, and the UCTxSTT bit must be set to generate a start condition. When a slave device sends
an acknowledgement, the UCTxSTT bit is cleared, and the data is received. Upon receiving an
8-bit data set, the UCRxIFG flag is set. Once the data is read from the buffer, the UCRxIFG flag is
cleared, and the next data can be received. If only a single 8-bit byte should be received, the controller
must set the UCTxSTP bit while the byte is received.
9.5.3 I
2
C CODE EXAMPLES
In this example, two MSP430 microcontrollers are connected via the I
2
C bus. The master reads
from the slave. Provided below is the master code, followed by the slave code. We have provided
the example in both C and assembly languages. The data from the slave transmitter begins at 0 and
increments with each transfer. The receive data is in R5 and is checked for validity. If the received
300 9. COMMUNICATION SYSTEMS
data is incorrect, the CPU is trapped and the P1.0 LED will stay on. The USCI_B0 RX interrupt
is used to know when new data has been received.
The master code in assembly:
;************************************************************************
;MSP430F54x Demo - USCI_B0 I2C Master RX single bytes from MSP430 Slave
;
;Description: This demo connects two MSP430’s via the I2C bus. The master
;reads from the slave. This is the MASTER CODE. The data from the slave
;transmitter begins at 0 and increments with each transfer. The received
;data is in R5 and is checked for validity. If the received data is
;incorrect, the CPU is trapped and the P1.0 LED will stay on. The USCI_B0
;RX interrupt is used to know when new data has been received.
;ACLK = n/a, MCLK = SMCLK = BRCLK = default DCO = ˜1.045MHz
;
; /|\ /|\
; MSP430F5438 10k 10k MSP430F5438
; slave | | master
; ----------------- | | -----------------
; -|XIN P3.1/UCB0SDA|<-|----+->|P3.1/UCB0SDA XIN|-
; | | | | | 32kHz
; -|XOUT | | | XOUT|-
; | P3.2/UCB0SCL|<-+------>|P3.2/UCB0SCL |
; | | | P1.0|--> LED
;
; M. Morales
; Texas Instruments Inc.
; September 2008
; Built with Code Composer Essentials v3.x
;************************************************************************
.cdecls C,LIST,"msp430x54x.h"
RXData .equ R5
RXCompare .equ R6
;------------------------------------------------------------------------
.global _main
.text ;Assemble to Flash memory
;------------------------------------------------------------------------

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