
192 4.2 System Processing
same time, “anticipating” one instruction result to generate the next one.
Depending on processor architectures, there can be 2, 4, or even 8 instruc-
tion pipelines. The processor clock speed can be slower, yet more work is
done at the same time.
The challenge with pipelining at the processor level is that this parallel-
ism only works to a certain extent. Executing a line of code as a series of
CPU instruction might require the result of previous instructions—if the
previous instruction is in another pipeline, the current pipeline needs to
stall and wait for the instruction results it depends upon.
As a short conclusion, single-core ...