//INTEGRAS/ELS/PAGINATION/ELSEVIER UK/PLC/3B2/FINALS-7-6-04/0750656794-CH03 1.3D – 322 – [315–323/9]
19.6.2004 9:22PM
(b) Should a second ISR be executed due to switch bounce within a few milli-seconds
of the first, then the following would happen if further X0 interrupts were not
temporarily disabled:
(i) The first ISR would display the contents of the cycle counter on the
7-segment displays and then reset D200.
(ii) The second ISR woul d now display the reset contents of D200, i.e. 00.
(iii) Since the cycle counter only displayed the correct count for a few
milli-seconds before displ aying 00, it would appear that no components
had been produced.
(c) To overcome switch bounc e, the following is carried out:
(i) Line 69 At the start of the ISR, the Instruction ...