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4. This in turn causes M110 to output a pulse for 1 scan time, which resets M100, the
Stack inhibit memory and re-enables the X0 input in the input data scan and transfer
section (Line 21).
5. Should X0 still be ON or come ON, then the transfer of the logical value correspond-
ing to X0, will be reloaded back onto the Stack.
6. The other stack inhibit memories, i.e. M101, M102, M103 and M104 will also be
reset, when their corresponding Y output is turned OFF.
33.6 Testing ^ QUEUE1
To test that the queue1 system operates as specified,