6.4 Synchronization Metrics for TDM and Synchronous Ethernet
A clock based on the physical layer signal is depicted in Figure 6.7. A comparator compares the clock input and clock output. In the case of phase comparator, the output will, in the long run, output the same number of clock cycles as goes in. The clock is thus called a phase-locked loop (PLL). Another method is to compare frequencies of the input and output. Because phase error accumulation is not an issue for base stations, as long as the frequency error remains within 16 ppb, phase lock is not necessary.
As the TDM specifications allow large short-term frequency variations, see Figure 6.9, a low-pass filter is needed to do averaging of the input phase or frequency. The most commonly used reference, 2 Mbit/s traffic signal needs about 1000-s averaging. Thus, the filter time constant should be of the same order of magnitude.
6.4.1 Stability Metric MTIE
Before going into the metric, let's quickly remind ourselves about the relationship between frequency and phase errors. Either or both terms will be used in this chapter depending on the context. Simply, the accumulated phase error over a time period is the average frequency error times the length of the time period. Frequency error is calculated as the difference between the measured and reference frequency, divided by the ...