Network-on-Chip

Network-on-Chip

by Santanu Kundu, Santanu Chattopadhyay
Released September 2018
Publisher(s): CRC Press
ISBN: 9781351831963

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Book description

Addresses the Challenges Associated with System-on-Chip Integration

Network-on-Chip: The Next Generation of System-on-Chip Integration

examines the current issues restricting chip-on-chip communication efficiency, and explores Network-on-chip (NoC), a promising alternative that equips designers with the capability to produce a scalable, reusable, and high-performance communication backbone by allowing for the integration of a large number of cores on a single system-on-chip (SoC). This book provides a basic overview of topics associated with NoC-based design: communication infrastructure design, communication methodology, evaluation framework, and mapping of applications onto NoC. It details the design and evaluation of different proposed NoC structures, low-power techniques, signal integrity and reliability issues, application mapping, testing, and future trends.

Utilizing examples of chips that have been implemented in industry and academia, this text presents the full architectural design of components verified through implementation in industrial CAD tools. It describes NoC research and developments, incorporates theoretical proofs strengthening the analysis procedures, and includes algorithms used in NoC design and synthesis. In addition, it considers other upcoming NoC issues, such as low-power NoC design, signal integrity issues, NoC testing, reconfiguration, synthesis, and 3-D NoC design.

This text comprises 12 chapters and covers:

  • The evolution of NoC from SoC—its research and developmental challenges
  • NoC protocols, elaborating flow control, available network topologies, routing mechanisms, fault tolerance, quality-of-service support, and the design of network interfaces
  • The router design strategies followed in NoCs
  • The evaluation mechanism of NoC architectures
  • The application mapping strategies followed in NoCs
  • Low-power design techniques specifically followed in NoCs
  • The signal integrity and reliability issues of NoC
  • The details of NoC testing strategies reported so far
  • The problem of synthesizing application-specific NoCs
  • Reconfigurable NoC design issues
  • Direction of future research and development in the field of NoC

Network-on-Chip: The Next Generation of System-on-Chip Integration

covers the basic topics, technology, and future trends relevant to NoC-based design, and can be used by engineers, students, and researchers and other industry professionals interested in computer architecture, embedded systems, and parallel/distributed systems.

Table of contents

  1. Cover
  2. Half Title
  3. Title Page
  4. Copyright Page
  5. Table of Contents
  6. Preface
  7. Authors
  8. 1. Introduction
    1. 1.1 System-on-Chip Integration and Its Challenges
    2. 1.2 SoC to Network-on-Chip: A Paradigm Shift
    3. 1.3 Research Issues in NoC Development
    4. 1.4 Existing NoC Examples
    5. 1.5 Summary
    6. References
  9. 2. Interconnection Networks in Network-on-Chip
    1. 2.1 Introduction
    2. 2.2 Network Topologies
      1. 2.2.1 Number of Edges
      2. 2.2.2 Average Distance
    3. 2.3 Switching Techniques
    4. 2.4 Routing Strategies
      1. 2.4.1 Routing-Dependent Deadlock
        1. 2.4.1.1 Deterministic Routing in M × N MoT Network
      2. 2.4.2 Avoidance of Message-Dependent Deadlock
    5. 2.5 Flow Control Protocol
    6. 2.6 Quality-of-Service Support
    7. 2.7 NI Module
    8. 2.8 Summary
    9. References
  10. 3. Architecture Design of Network-on-Chip
    1. 3.1 Introduction
    2. 3.2 Switching Techniques and Packet Format
    3. 3.3 Asynchronous FIFO Design
    4. 3.4 GALS Style of Communication
    5. 3.5 Wormhole Router Architecture Design
      1. 3.5.1 Input Channel Module
      2. 3.5.2 Output Channel Module
    6. 3.6 VC Router Architecture Design
      1. 3.6.1 Input Channel Module
      2. 3.6.2 Output Links
        1. 3.6.2.1 VC Allocator
        2. 3.6.2.2 Switch Allocator
    7. 3.7 Adaptive Router Architecture Design
    8. 3.8 Summary
    9. References
  11. 4. Evaluation of Network-on-Chip Architectures
    1. 4.1 Evaluation Methodologies of NoC
      1. 4.1.1 Performance Metrics
      2. 4.1.2 Cost Metrics
    2. 4.2 Traffic Modeling
    3. 4.3 Selection of Channel Width and Flit Size
    4. 4.4 Simulation Results and Analysis of MoT Network with WH Router
      1. 4.4.1 Accepted Traffic versus Offered Load
      2. 4.4.2 Throughput versus Locality Factor
      3. 4.4.3 Average Overall Latency at Different Locality Factors
      4. 4.4.4 Energy Consumption at Different Locality Factors
    5. 4.5 Impact of FIFO Size and Placement in Energy and Performance of a Network
    6. 4.6 Performance and Cost Comparison of MoT with Other NoC Structures Having WH Router under Self-Similar Traffic
      1. 4.6.1 Network Area Estimation
      2. 4.6.2 Network Aspect Ratio
      3. 4.6.3 Performance Comparison
        1. 4.6.3.1 Accepted Traffic versus Offered Load
        2. 4.6.3.2 Throughput versus Locality Factor
        3. 4.6.3.3 Average Overall Latency under Localized Traffic
      4. 4.6.4 Comparison of Energy Consumption
    7. 4.7 Simulation Results and Analysis of MoT Network with Virtual Channel Router
      1. 4.7.1 Throughput versus Offered Load
      2. 4.7.2 Latency versus Offered Load
      3. 4.7.3 Energy Consumption
      4. 4.7.4 Area Required
    8. 4.8 Performance and Cost Comparison of MoT with Other NoC Structures Having VC Router
      1. 4.8.1 Accepted Traffic versus Offered Load
      2. 4.8.2 Throughput versus Locality Factor
      3. 4.8.3 Average Overall Latency under Localized Traffic
      4. 4.8.4 Energy Consumption
      5. 4.8.5 Area Overhead
    9. 4.9 Limitations of Tree-Based Topologies
    10. 4.10 Summary
    11. References
  12. 5. Application Mapping on Network-on-Chip
    1. 5.1 Introduction
    2. 5.2 Mapping Problem
    3. 5.3 ILP Formulation
      1. 5.3.1 Other ILP Formulations
    4. 5.4 Constructive Heuristics for Application Mapping
      1. 5.4.1 Binomial Merging Iteration
      2. 5.4.2 Topology Mapping and Traffic Surface Creation
      3. 5.4.3 Hardware Cost Optimization
    5. 5.5 Constructive Heuristics with Iterative Improvement
      1. 5.5.1 Initialization Phase
      2. 5.5.2 Shortest Path Computation
      3. 5.5.3 Iterative Improvement Phase
      4. 5.5.4 Other Constructive Strategies
    6. 5.6 Mapping Using Discrete PSO
      1. 5.6.1 Particle Structure
      2. 5.6.2 Evolution of Generations
      3. 5.6.3 Convergence of DPSO
      4. 5.6.4 Overall PSO Algorithm
      5. 5.6.5 Augmentations to the DPSO
        1. 5.6.5.1 Multiple PSO
        2. 5.6.5.2 Initial Population Generation
      6. 5.6.6 Other Evolutionary Approaches
    7. 5.7 Summary
    8. References
  13. 6. Low-Power Techniques for Network-on-Chip
    1. 6.1 Introduction
    2. 6.2 Standard Low-Power Methods for NoC Routers
      1. 6.2.1 Clock Gating
      2. 6.2.2 Gate Level Power Optimization
      3. 6.2.3 Multivoltage Design
        1. 6.2.3.1 Challenges in Multivoltage Design
      4. 6.2.4 Multi-VT Design
      5. 6.2.5 Power Gating
    3. 6.3 Standard Low-Power Methods for NoC Links
      1. 6.3.1 Bus Energy Model
      2. 6.3.2 Low-Power Coding
      3. 6.3.3 On-Chip Serialization
      4. 6.3.4 Low-Swing Signaling
    4. 6.4 System-Level Power Reduction
      1. 6.4.1 Dynamic Voltage Scaling
        1. 6.4.1.1 History-Based DVS
        2. 6.4.1.2 Hardware Implementation
        3. 6.4.1.3 Results and Discussions
      2. 6.4.2 Dynamic Frequency Scaling
        1. 6.4.2.1 History-Based DFS
        2. 6.4.2.2 DFS Algorithm
        3. 6.4.2.3 Link Controller
        4. 6.4.2.4 Results and Discussions
      3. 6.4.3 VFI Partitioning
      4. 6.4.4 Runtime Power Gating
    5. 6.5 Summary
    6. References
  14. 7. Signal Integrity and Reliability of Network-on-Chip
    1. 7.1 Introduction
    2. 7.2 Sources of Faults in NoC Fabric
      1. 7.2.1 Permanent Faults
      2. 7.2.2 Faults due to Aging Effects
        1. 7.2.2.1 Negative-Bias Temperature Instability
        2. 7.2.2.2 Hot Carrier Injection
      3. 7.2.3 Transient Faults
        1. 7.2.3.1 Capacitive Crosstalk
        2. 7.2.3.2 Soft Errors
        3. 7.2.3.3 Some Other Sources of Transient Faults
    3. 7.3 Permanent Fault Controlling Techniques
    4. 7.4 Transient Fault Controlling Techniques
      1. 7.4.1 Intra-Router Error Control
        1. 7.4.1.1 Soft Error Correction
      2. 7.4.2 Inter-Router Link Error Control
        1. 7.4.2.1 Capacitive Crosstalk Avoidance Techniques
        2. 7.4.2.2 Error Detection and Retransmission
        3. 7.4.2.3 Error Correction
    5. 7.5 Unified Coding Framework
      1. 7.5.1 Joint CAC and LPC Scheme (CAC + LPC)
      2. 7.5.2 Joint LPC and ECC Scheme (LPC + ECC)
      3. 7.5.3 Joint CAC and ECC Scheme (CAC + ECC)
      4. 7.5.4 Joint CAC, LPC, and ECC Scheme (CAC + LPC + ECC)
    6. 7.6 Energy and Reliability Trade-Off in Coding Technique
    7. 7.7 Summary
    8. References
  15. 8. Testing of Network-on-Chip Architectures
    1. 8.1 Introduction
    2. 8.2 Testing Communication Fabric
      1. 8.2.1 Testing NoC Links
      2. 8.2.2 Testing NoC Switches
      3. 8.2.3 Test Data Transport
      4. 8.2.4 Test Transport Time Minimization—A Graph Theoretic Formulation
        1. 8.2.4.1 Unicast Test Scheduling
        2. 8.2.4.2 Multicast Test Scheduling
    3. 8.3 Testing Cores
      1. 8.3.1 Core Wrapper Design
      2. 8.3.2 ILP Formulation
      3. 8.3.3 Heuristic Algorithms
      4. 8.3.4 PSO-Based Strategy
        1. 8.3.4.1 Particle Structure and Fitness
        2. 8.3.4.2 Evolution of Generations
    4. 8.4 Summary
    5. References
  16. 9. Application-Specific Network-on-Chip Synthesis
    1. 9.1 Introduction
    2. 9.2 ASNoC Synthesis Problem
    3. 9.3 Literature Survey
    4. 9.4 System-Level Floorplanning
      1. 9.4.1 Variables
        1. 9.4.1.1 Independent Variables
        2. 9.4.1.2 Dependent Variables
      2. 9.4.2 Objective Function
      3. 9.4.3 Constraints
      4. 9.4.4 Constraints for Mesh Topology
    5. 9.5 Custom Interconnection Topology and Route Generation
      1. 9.5.1 Variables
        1. 9.5.1.1 Independent Variables
        2. 9.5.1.2 Derived Variables
      2. 9.5.2 Objective Function
      3. 9.5.3 Constraints
    6. 9.6 ASNoC Synthesis with Flexible Router Placement
      1. 9.6.1 ILP for Flexible Router Placement
        1. 9.6.1.1 Variables
        2. 9.6.1.2 Objective Function
        3. 9.6.1.3 Constraints
      2. 9.6.2 PSO for Flexible Router Placement
        1. 9.6.2.1 Particle Structure and Fitness Function
        2. 9.6.2.2 Local and Global Bests
        3. 9.6.2.3 Evolution of Generation
        4. 9.6.2.4 Swap Operator
        5. 9.6.2.5 Swap Sequence
    7. 9.7 Summary
    8. References
  17. 10. Reconfigurable Network-on-Chip Design
    1. 10.1 Introduction
    2. 10.2 Literature Review
    3. 10.3 Local Reconfiguration Approach
      1. 10.3.1 Routers
      2. 10.3.2 Multiplexers
      3. 10.3.3 Selection Logic
      4. 10.3.4 Area Overhead
      5. 10.3.5 Design Flow
        1. 10.3.5.1 Construction of CCG
        2. 10.3.5.2 Mapping of CCG
        3. 10.3.5.3 Configuration Generation
      6. 10.3.6 ILP-Based Approach
        1. 10.3.6.1 Parameters and Variables
        2. 10.3.6.2 Objective Function
        3. 10.3.6.3 Constraints
      7. 10.3.7 PSO Formulation
        1. 10.3.7.1 Particle Formulation and Fitness Function
      8. 10.3.8 Iterative Reconfiguration
    4. 10.4 Topology Reconfiguration
      1. 10.4.1 Modification around Routers
      2. 10.4.2 Reconfiguration Architecture
        1. 10.4.2.1 Application Mapping
        2. 10.4.2.2 Core-to-Network Mapping
        3. 10.4.2.3 Topology and Route Generation
    5. 10.5 Link Reconfiguration
      1. 10.5.1 Estimating Channel Bandwidth Utilization
    6. 10.6 Summary
    7. References
  18. 11. Three-Dimensional Integration of Network-on-Chip
    1. 11.1 Introduction
    2. 11.2 3D Integration: Pros and Cons
      1. 11.2.1 Opportunities of 3D Integration
      2. 11.2.2 Challenges of 3D Integration
    3. 11.3 Design and Evaluation of 3D NoC Architecture
      1. 11.3.1 3D Mesh-of-Tree Topology
        1. 11.3.1.1 Number of Directed Edges
        2. 11.3.1.2 Average Distance
      2. 11.3.2 Performance and Cost Evaluation
        1. 11.3.2.1 Network Area Estimation
        2. 11.3.2.2 Network Aspect Ratio
      3. 11.3.3 Simulation Results with Self-Similar Traffic
        1. 11.3.3.1 Accepted Traffic versus Offered Load
        2. 11.3.3.2 Throughput versus Locality Factor
        3. 11.3.3.3 Average Overall Latency under Localized Traffic
        4. 11.3.3.4 Energy Consumption
      4. 11.3.4 Simulation Results with Application-Specific Traffic
    4. 11.4 Summary
    5. References
  19. 12. Conclusions and Future Trends
    1. 12.1 Conclusions
    2. 12.2 Future Trends
      1. 12.2.1 Photonic NoC
      2. 12.2.2 Wireless NoC
    3. 12.3 Comparison between Alternatives
    4. References
  20. Index

Product information

  • Title: Network-on-Chip
  • Author(s): Santanu Kundu, Santanu Chattopadhyay
  • Release date: September 2018
  • Publisher(s): CRC Press
  • ISBN: 9781351831963