8.1 Introduction
Testing network-on-chip (NoC) architectures is very challenging. In fact, the problem is difficult for any system-on-chip (SoC) design paradigm. In SoC, the intellectual property (IP) cores are integrated into a system design. A SoC integrator does not possess the detailed knowledge about the implementation of individual cores in the system. The netlist-level description, required for running a test generation tool, is generally not provided by the core vendors due to IP rights. The layout-level description of the cores provided by the vendors cannot act as input for the test generation process. Hence, the system integrator has to depend upon the test sets provided by the core ...
