[bib01_1]  A. Adriahantenaina, H. Charlery, A. Greiner, L. Mortiezand and C. Zeferino, “SPIN: A Scalable, Packet Switched, On-Chip Micro-network,” DATE – Design, Automation and Test in Europe Conference and Exhibition, 2003, pp. 70–73 .
[bib01_2]  A.H. Ajami, K. Banerjee and M. Pedram, “Modeling and Analysis of Nonuniform Substrate Temperature Effects on Global ULSI Interconnects,” IEEE Transactions on CAD, Vol. 24, No. 6, June 2005, pp. 849–861.
[bib01_3]  H. Bakoglu, Circuits, Interconnections, and Packaging for VLSI, Addison-Wesley, Upper Saddle River, NJ, 1990.
[bib01_4]  L. Benini, A. Bogliolo and G. De Micheli, “A Survey of Design Techniques for System-Level Dynamic Power Management,” IEEE Transactions on Very Large-Scale Integration ...