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On-Chip Communication Architectures by Nikil Dutt, Sudeep Pasricha

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Chapter 4. Models for Performance Exploration

On-chip communication architectures have numerous sources of delay due to signal propagation along the wires, synchronization (e.g., handshaking), transfer modes (e.g., pipeline access, burst transfer, etc.), arbitration mechanisms for congestion management, cross-bridge transfers, and data packing/unpacking at the interfaces. These communication delays can significantly influence the performance of system-on-chip (SoC) applications, and are in fact, a major cause of bottlenecks in many designs. It is therefore important to consider these delays when exploring SoC applications, in order to get an accurate estimation of the system performance. Figure 4.1 shows where communication architecture performance ...

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