
OEQ section. Figure 9.67 shows more details of this OEQ. This design has only
1 2 and 2 1 couplers , and thus, according to the Flat-Top Filter Construction
Theorem, it has intrinsic loss when used as a TODC.
Parallel Arrangement: Another way to construct a tapped delay line is to use
a parallel arrangement of waveguides of different lengths and is called a transversal
filter. An example in silica is shown in Figure 9.68 [92], and an example in InP is
shown in Figure 9.69 [93]. Again, because transversal filters contain only 1 N or
N 1 couplers, they have intrinsic loss when used as TODCs. The intrinsic loss
Time
Power
Control magnitude of post-cursor ...