with WDM approaches regarding the cost for the terminal equipment. This is
possible only if components are matured and integration is progressing like
indicated in the chapter on components for 100 Gbit/s systems.
REFERENCES
[1] K. Schuh, B. Junginger, E. Lach et al., “85.4 Gbit/s ETDM Receiver with Full Rate Electronic
Clock Recovery Circuit,” in Proc. ECOC 2004, Post-deadline paper Th4.1.1, 2004.
[2] K. Schuh, B. Junginger, H. Rempp et al., “85.4 Gbit/s ETDM Transmission over 401 km SSMF
Applying UFEC,” in Proc. ECOC 2005, Post-deadline paper Th4.1.4, 2004.
[3] IEEE 802, High speed study group (HSSG): http://grouper.ieee.org/groups/802/3/hssg/public/
index.html
[4] A. Schmid-Egger and A. Kirsta
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dter, “Ethernet in Core Networks: A Technical and Economical ...