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Optical Sources, Detectors, and Systems by Robert H. Kingston

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8.4 Charge-Coupled Device (CCD) Arrays 187
q V 1.6x10-^^
The dynamic range of the detectors is determined by the storage capac-
itance at each diode, consisting of the detector internal capacitance plus,
if desired, an external capacitor. With a net capacitance of
1
pf and a
maximum voltage swing of 5 V, the net electron storage becomes N =
CV/q
=
3 xlO^electrons, or a dynamic range of more than 30l If the
same array is operated at long wavelengths and is background-limited,
then the background electron count might be set at 10^
electrons,
with a
resultant (NEE)BiOi 3.23 x l(fi and a net NEE of 3A x
1(P
including
the read-out contribution of Eq. (8.8). It is in this latter mode of oper-
ation that array uniformity becomes critical and it is often necessary to
post-process the data using individual detector calibration data. Two-
dimensional array readout is accomplished by sequential readout of each
row of detectors in the array.
8.4 Charge-Coupled Device (CCD) Arrays
The read-out techniques discussed in the preceding sections can be
performed using an integrated detector and read-out array in a semi-
conductor chip. This technique is particularly attractive for siUcon
detectors because of the large number of elements and uniformity
available with current VLSI technology. Various integrated detection
and read-out techniques are discussed in (Waynant and
Ediger,
1994, Ch.
18) and
(Accetta
and
Shumaker,
1993, Vol 3) and the most sensitive and
frequently used is the charge-coupled device or CCD.
Figure 8.7 is the energy diagram for a
p-type
silicon metal-oxide
semiconductor (MOS) structure with two different positive voltages on
the metal electrode. The heavy lines have the highest positive potential
and therefore attract electrons into the well adjacent to the oxide layer.
These electrons are produced by thermal generation (dark current), by
photoionization (photocurrent), or by transfer from an adjacent region
(dimension into the paper) at a lower positive voltage, as shown by the
light-lined diagram. An alternative representation is in Figure 8.8,
which shows the phase diagram for the electrode voltage drive, a short
188
Systems IL: Imaging
oxide
metal
+++
U,
u
u
p-type
silicon
Figure 8.7 Energy diagram for two adjacent
CCD
wells.
The darker lines show the more
positive metal electrode
cross-section of aCCD structure, and the potential changes as the elec-
tron charge packet is transferred to an adjacent electrode. In an imaging
mode, the incident light produces electrons that travel to the nearest
deep well and, after a frame time, the charges are "clocked" one pixel or
three electrode units to the right, and in the two-dimensional structure of
V
^UJd Lid bi^ L^B
Figure 8.8 Phase diagram for electrode voltage drive,
CCD
cross-section, and associated
potentials
8.4 Charge-Coupled Device (CCD) Arrays
189
1111
nil
ill!
lODDK
IDDDDK
1DH[
IDMD
Mil
ill
mi
Hi
HI
Hi
HI
DD
IB
ID
m
i
i
Figure 8.9 CCD imaging array showing read-out sequence
Figure 8.9, stored in a column register of CCD wells. The column is then
read out to a charge-sensing electrode and then the sequence repeated
until the full frame has been read out. The illun\ination may fall on the
back of the thin silicon substrate or on the surface if the metal electrodes
are transparent. Since the readout takes a full frame time, many CCD
imagers are twice the image size and a full frame is transferred to an
unilluminated region and then read out while the next frame is being
imaged. The key to successful operation is a high transfer efficiency
from well to well, that is, negligible trapping or loss of electrons. This is
critically dependent on the oxide-silicon interface in the "surface-chan-
nel"
device we discuss here. It is also possible to build "buried-channel"
structures where the well is isolated from the oxide by a potential barrier
(Howes and Morgan, 1979). In addition, two-phase rather than three-
phase operation may be accomplished by varying the impurity doping
along each gate electrode.
The sensitivity of the CCD can be extremely high because of the
single charge sensor electrode and the resultant opportunity for a low
capacitance. The output circuit, as shown in Figure 8.10, is a resetting
integrator with an FET switch and an FET input stage amplifier. Both
FETs are integrated on-chip thus minimizing the capacitance. The sen-
sor electrode is initially set to
+V
with the switch closed, then the switch

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