PCI Express System Architecture

Figures

1-1 Comparison of Performance Per Pin for Various Buses

1-2 33 MHz PCI Bus Based Platform

1-3 Typical PCI Burst Memory Read Bus Cycle

1-4 33 MHz PCI Based System Showing Implementation of a PCI-to-PCI Bridge

1-5 PCI Transaction Model

1-6 PCI Bus Arbitration

1-7 PCI Transaction Retry Mechanism

1-8 PCI Transaction Disconnect Mechanism

1-9 PCI Interrupt Handling

1-10 PCI Error Handling Protocol

1-11 Address Space Mapping

1-12 PCI Configuration Cycle Generation

1-13 256 Byte PCI Function Configuration Register Space

1-14 Latest Generation of PCI Chipsets

1-15 66 MHz PCI Bus Based Platform

1-16 66 MHz/133 MHz PCI-X Bus Based Platform

1-17 Example PCI-X Burst Memory Read Bus Cycle

1-18 PCI-X Split Transaction Protocol

1-19 Hypothetical PCI-X 2.0 Bus Based Platform ...