Book description
This IBM® Redbooks® publication focuses on gathering the correct technical information, and laying out simple guidance for optimizing code performance on IBM POWER8™ systems that run the AIX®, IBM i, or Linux operating systems. There is much straightforward performance optimization that can be performed with a minimum of effort and without extensive previous experience or in-depth knowledge.
The POWER8 processor contains many new and important performance features, such as support for eight hardware threads in each core and support for transactional memory. POWER8 is a strict superset of IBM POWER7+™, and so all of the performance features of POWER7+, such as multiple page sizes, also appear in POWER8. Much of the technical information and guidance for optimizing performance on POWER8 presented in this guide also applies to POWER7+ and earlier processors, except where the guide explicitly indicates that a feature is new in POWER8.
This guide strives to focus on optimizations that tend to be positive across a broad set of IBM POWER® processor chips and systems. Specific guidance is given for the POWER8 processor; however, the general guidance is applicable to the IBM POWER7+, IBM POWER7®, IBM POWER6®, IBM POWER5, and even to earlier processors.
This guide is directed to personnel who are responsible for performing migration and implementation activities on IBM POWER8-based servers. This includes system administrators, system architects, network administrators, information architects, and database administrators (DBAs).
Table of contents
- Front cover
- Notices
- Preface
- Chapter 1. Optimization and tuning on IBM POWER8
-
Chapter 2. The POWER8 processor
- 2.1 Introduction to the POWER8 processor
-
2.2 Using POWER8 features
- 2.2.1 Multi-core and multi-thread
- 2.2.2 Multipage size support: Page sizes (4 KB, 64 KB, 16 MB, and 16 GB)
- 2.2.3 Efficient use of cache and memory
- 2.2.4 Transactional memory (TM)
- 2.2.5 Vector Scalar eXtension (VSX)
- 2.2.6 Decimal floating point
- 2.2.7 In-core cryptography and integrity enhancements
- 2.2.8 On-chip accelerators
- 2.2.9 Storage synchronization (sync, lwsync, lwarx, stwcx, and eieio)
- 2.2.10 Fixed-point load and store quadword instructions
- 2.2.11 Instruction fusion
- 2.2.12 Event-based branches (or user-level fast interrupts)
- 2.2.13 Power management and system performance
- 2.3 Related publications
- Chapter 3. The POWER Hypervisor
-
Chapter 4. AIX
- 4.1 Introduction
- 4.2 Using Power features with AIX
-
4.3 AIX operating system-specific optimizations
- 4.3.1 Malloc
- 4.3.2 Pthread tunables
- 4.3.3 pollset
- 4.3.4 File system performance benefits
- 4.3.5 Direct I/O
- 4.3.6 Concurrent I/O (CIO)
- 4.3.7 Asynchronous I/O
- 4.3.8 I/O completion ports
- 4.3.9 shmat versus mmap
- 4.3.10 Large segment tunable aliasing (LSA)
- 4.3.11 64-bit versus 32-bit ABIs
- 4.3.12 Sleep and wake-up primitives (thread_wait and thread_post)
- 4.3.13 Shared versus private loads
- 4.3.14 Workload partitions (WPARs) shared License Program Product (LPP) installs
- 4.4 AIX preferred practices
- 4.5 Related publications
- Chapter 5. IBM i
- Chapter 6. Linux
- Chapter 7. Compilers and optimization tools for C, C++, and Fortran
-
Chapter 8. Java
- 8.1 Java levels
- 8.2 32-bit versus 64-bit Java
-
8.3 Memory and page size considerations
- 8.3.1 Medium and large pages for Java heap and code cache
- 8.3.2 Configuring large pages for Java heap and code cache
- 8.3.3 Prefetching
- 8.3.4 Compressed references
- 8.3.5 JIT code cache
- 8.3.6 Shared classes
- 8.3.7 In-core Advanced Encryption Standard (AES) acceleration
- 8.3.8 Transactional memory (TM)
- 8.3.9 Runtime instrumentation
- 8.4 Java garbage collection tuning
- 8.5 Application scaling
- 8.6 Related publications
-
Chapter 9. DB2
- 9.1 DB2 and the POWER processor
- 9.2 Taking advantage of the POWER processor
- 9.3 Capitalizing on the compilers and optimization tools for POWER
- 9.4 Capitalizing on POWER virtualization
- 9.5 Capitalizing on the AIX system libraries
- 9.6 Capitalizing on performance tooling
- 9.7 Conclusion
- 9.8 Related publications
- Chapter 10. WebSphere Application Server
- Appendix A. Analyzing malloc usage under AIX
- Appendix B. Performance tooling and empirical performance analysis
- Back cover
-
IBM System x Reference Architecture for Hadoop: IBM InfoSphere BigInsights Reference Architecture
- Introduction
- Business problem and business value
- Reference architecture use
- Requirements
- InfoSphere BigInsights predefined configuration
- InfoSphere BigInsights HBase predefined configuration
- Deployment considerations
- Customizing the predefined configurations
- Predefined configuration bill of materials
- References
- The team who wrote this paper
- Now you can become a published author, too!
- Stay connected to IBM Redbooks
- Notices
Product information
- Title: Performance Optimization and Tuning Techniques for IBM Processors, including IBM POWER8
- Author(s):
- Release date: July 2014
- Publisher(s): IBM Redbooks
- ISBN: None
You might also like
book
Performance Optimization and Tuning Techniques for IBM Power Systems Processors Including IBM POWER8
This IBM® Redbooks® publication focuses on gathering the correct technical information, and laying out simple guidance …
book
IBM Power Systems HMC Implementation and Usage Guide
The IBM® Hardware Management Console (HMC) provides to systems administrators a tool for planning, deploying, and …
book
IBM AIX Version 7.1 Differences Guide
This IBM® Redbooks® publication focuses on the enhancements to IBM AIX® Version 7.1 Standard Edition. It …
book
IBM PowerVC Version 2.0 Introduction and Configuration
IBM® Power Virtualization Center (IBM® PowerVC™) is an advanced enterprise virtualization management offering for IBM Power …