Physical Design for 3D Integrated Circuits

6	Power and Signal Integrity Challenges in 3D Systems-on-Chip Emre Salman

CONTENTS

Abstract

6.1    Introduction

6.2    TSV Technologies and Implications to Power/Signal Integrity

6.2.1    Via-First TSV Technology

6.2.2    Via-Middle TSV Technology

6.2.3    Via-Last TSV Technology

6.3    System-Wide 3D Power Integrity

6.3.1    Case Study: Power Distribution in a Nine-Plane 3D Processor-DRAM Stack

6.3.1.1    Architecture

6.3.1.2    Power Distribution Network Model

6.3.1.3    Results

6.3.2    Decoupling Capacitors for Power-Gated 3D-ICs

6.3.2.1    Reconfigurable Topology

6.3.2.2    Evaluation Setup

6.3.2.3    Results

6.4    System-Wide 3D Signal Integrity

6.4.1    Efficient Analysis of TSV-to-Transistor Noise Coupling

6.4.1.1    Distributed ...