Physical Design for 3D Integrated Circuits

7	Design Methodology for TSV-Based 3D Clock Networks Taewhan Kim and Heechun Park

CONTENTS

Abstract

7.1    Introduction

7.2    3D Clock Tree Synthesis

7.2.1    Design Flow

7.2.2    3D-MMM-Based CTS

7.2.3    MMM-3D and NN-3D Based CTS

7.2.4    Layer Embedding

7.2.5    Routing

7.3    Clock Tree Synthesis with Pre-Bond Testability

7.3.1    Basics

7.3.2    Main Issues in Pre-Bond Testability

7.3.3    Pre-Bond Testable 3D Clock Tree

7.3.4    Additional Issues

7.4    Clock TSV Fault-Tolerant Techniques

7.4.1    Basics

7.4.2    Redundant TSV Methods

7.4.3    Advanced TSV Fault-Tolerant Techniques

7.4.4    Additional Issues

7.5    Variation Tolerant Techniques and Others

7.5.1    Thermal Variation Aware CTS

7.5.2    TSV-Stress Aware CTS

7.5.3    On-Package ...