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Power Integrity Analysis and Management for Integrated Circuits by Donald Bennett, Raj Nair

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Chapter 9. Power Integrity Management in Integrated Circuits and Systems

Masanori Hashimoto and Raj Nair

Prior chapters have discussed many techniques for mitigating power integrity (PI) degradation in integrated circuits (ICs). Reducing interconnect resistance and inductance through integrated circuit manufacturing process changes provides the most benefit. Such changes include increased metal interconnect layers, the introduction of copper into chips, and disciplined front-end planning and physical design. Transient on-chip noise can also be reduced through the judicious inclusion of on-chip decoupling capacitance and the optimized placement of this capacitance as well as functional blocks. Techniques for managing on-chip PI also include platform ...

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