O'Reilly logo

Real World FPGA Design with Verilog by Ken Coffman - President, Bytech Services

Stay ahead with the world's most comprehensive technology and business learning platform.

With Safari, you learn the way you learn best. Get unlimited access to videos, live online training, learning paths, books, tutorials, and more.

Start Free Trial

No credit card required

Chapter 4 More Digital Circuits: Counters, ROMs, and RAMs

This chapter presents an assortment of digital designs implemented with Verilog.

RIPPLE COUNTERS

The most common (generic) counter is a ripple counter, so described because the output ripples from stage to stage. If we create a Verilog counter like Listing 4-1, using the binary-counter option in Exemplar Logic LeonardoSpectrum’s Input File menu as shown in Figure 4-1, we’ll find the result is a synchronous binary counter.

Listing 4-1 Verilog Code for Simple Counter

  module ripple1 (count_out, clk, reset);        input                   clk, reset;        output                  count_out;        reg             [3:0] count_out;        always @ (posedge clk or posedge reset)         ...

With Safari, you learn the way you learn best. Get unlimited access to videos, live online training, learning paths, books, interactive tutorials, and more.

Start Free Trial

No credit card required