Memory Models for Embedded Multicore Architecture
Gitu Jain, Software Engineer, Synopsys
Chapter Outline
Translation lookaside buffer (TLB)
Memory structure of multicore architecture
Non-uniform memory access (NUMA)
Distributed memory architecture
Cache memory in multicore chips
Directory-based cache coherence protocol
Snoopy cache coherence protocol
Cache-related performance issues
Get Real World Multicore Embedded Systems now with the O’Reilly learning platform.
O’Reilly members experience books, live events, courses curated by job role, and more from O’Reilly and nearly 200 top publishers.