Chapter 6
Wireless Synthesizers
6.1 Introduction
Increasing integration has drastically narrowed the range of component choices open to wireless synthesizer designers. The design of a high-performance synthesizer is largely reduced to selecting the most advanced synthesizer IC and, if the synthesizer uses a phase-locked loop, designing or obtaining the best VCO. This chapter covers synthesizer theory, evaluation, and design, including PLL and direct digital synthesis (DDS) techniques. Going into all the details of frequency synthesizers would be beyond the scope of this book. For depth and background on this subject, we recommend Ref. [1].
6.2 Phase-Locked Loops
6.2.1 PLL Basics
Figure 6.1 shows a complete PLL synthesizer block diagram indicating the areas over which the designer actually has control. Once the VCO signal has been translated from analog to quasidigital (square-wave) form in circuitry similar to a line receiver, the synthesizer IC takes over. The VCO receives an analog control signal that results from the integration of digital pulses from a phase/frequency discriminator. Modern phase/frequency discriminators, which are part of the PLL IC, use edge-triggered loop locks and generate correcting pulses of either positive or negative sign. The output portion of such a phase detector is frequently referred to as a charge pump because the resulting dc control voltage, which ultimately determines the oscillator frequency, is processed by a loop filter containing at least ...
