Servicing Personal Computers, 3rd Edition

Microcomputer systems 31

Table 1.3 shows the truth table for the address lines and decoding logic of the memory

device. This table assumes that the most significant part of the address (high order) appears first

and is decoded to the appropriate row while the least significant (low order) part appears

second and is decoded to the appropriate column. The table shows the logic states for three

address locations: 0, 255, and 16 383 (0000H, 00FFH, and 3FFFH respectively).

Table 1.3 Multiplexed address decoding for a typical memory cell matrix

Order

High

Low

High

Low

High

Low

A6 A5 A4 A3 A2 A1 AO

0 0 0 0 0 0 0

0 0 0 0 0 0 0

0 0 0 0 0 0 1

111111