Servicing Personal Computers, 3rd Edition

Servicing the IBM

PC

and compatibles 241

5. Upon receiving the INTA pulse from the processor, the highest priority ISR bit is set and the

corresponding IRR bit is reset.

6. The processor then initiates a second interrupt acknowledge (INTA) pulse. During this

second period for which the INTA line is taken low, the 8259 outputs a pointer on the data

bus to be read by the processor.

The internal architecture and pin connections for the 8259A are shown in Figures 6.24 and

6.25 respectively.

cs

WR

ÏÏD

D

7

D

6

D

5

D

4

D

3

D

2

D

1

D

0

C

C

C

c

c

c

c

c

c

c

c

CASO

C

CAS

1

GND

c

c

1

2

3

4

5

6

7

8

9

10

11

12

13

14

^^r

28

27

26

25

24

23

22

8259A21

20

19

18

17