As cycle times in high-performance digital systems shrink faster than simple process improvement allows, sequencing overhead consumes an increasing fraction of the clock period. Engineers allocate ever more effort and chip routing resources to the clock network, yet clock skew is becoming a more serious concern. Systems using static logic and edge-triggered flip-flops must budget this clock skew in every clock cycle. Worse yet, aggressive systems attempting to use domino circuits for greater speed budget this clock skew in every half-cycle, or twice in every clock cycle! Moreover, designers have difficulty completely utilizing shrinking clock cycles. The fraction of a gate delay unused at the end of each cycle or half-cycle represents ...

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