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Skew-Tolerant Circuit Design by David Harris

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Bibliography

[1] Nov Bailey, D., Benschneider, B. Clocking Design and Analysis for a 600-MHz Alpha Microprocessor. IEEE J. Solid-State Circuits. 1998;vol. 33(no. 11):1627–1633.

[2] Feb. Bearden, D., et al. A 133 MHz 64b Four-Issue CMOS Microprocessor. ISSCC Dig. Tech. Papers. 1995:174–175.

[3] Feb. Benschneider, B., et al. A lGHz Alpha Microprocessor. ISSCC Dig. Tech. Papers. 2000:86–87.

[4] Oct Boonstra, L., Lambrechtse, C., Salters, R. A 4096-b One-Transistor per Bit Random-Access Memory with Internal Timing and Low Dissipation. IEEE J. Solid-State Circuits. 1973;vol. SC-8(no. 5,):305–310.

[5] Feb. Bowhill, W., et al. A 300 MHz 64 b Quad-Issue CMOS Microprocessor. ISSCC Dig. Tech. Papers. 1995:182–183.

[6] Bowhill, W., et al. Circuit Implementation ...

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