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Skew-Tolerant Circuit Design by David Harris

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Index

A

aggressor, 88, 89
defined, 88
spacing between victim, 90
Alpha 21064, 62
dynamic latches, 62
TSPC latches, 138
Alpha 21164
blocks of domino, 38
blocks of static logic, 38
defined, 24
dynamic latches, 62
latch elimination, 138
overlapping clocks, 97
sequencing overhead in, 24
static latches, 62
transmission gate latch, 54, 129
Alpha 21264
keepers, 96
min-delay risks, 139
static memory elements, 62
alpha particles, 92
arrival times, 168, 169, 172, 210
asynchronous design, 37
clocking overhead and, 37
“zero-overhead, ”, 96

C

capacitive coupling, 88–90
capacitive voltage divider equation, 86
charge injection, 92
charge sharing, 52, 86–88, 131
circuit methodology, 103–139
clock chopper, 55, 56
clock domain ...

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