UltraSPARC Interconnect Architectures
The UltraSPARC I and UltraSPARC II processors have far higher bandwidth requirements than do the previous generation SuperSPARC systems. A completely new approach to interconnect technologies was developed to support them. In this section, I first describe the interconnect architectures, followed by the system implementations and packaging.
The UltraSPARC Port Architecture Switched Interconnect
Bus architectures like MBus (and many other buses in use today) use each wire to carry data and address information from every device on the bus. This use makes the wire long and makes the protocol complex. It also reduces data bandwidth because the wire has to carry address information in between the data transfers. ...
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