Sun Performance and Tuning: Java™ and the Internet, Second Edition

I/O Caches

If an I/O device is performing a DVMA transfer—for example, a disk controller is writing data into memory—the CPU can continue other operations while the data is transferred. Care must be taken to ensure that the data written to by the I/O device is not also in the cache, otherwise inconsistencies can occur. On older Sun systems and the 4/260 and SPARC system 300, every word of I/O is passed through the cache. A lot of I/O activity slows down the CPU because the CPU cannot access the cache for a cycle. The SPARC system 400 has an I/O cache that holds 128 lines of 32 bytes and checks its validity with the CPU cache once for each line. The interruption to the CPU is reduced from once every 4 bytes to once every 32 bytes. The other benefit ...